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Exploiting Approximation for Run-time Resource Management of embedded HMPs

ACM Transactions on embedded Computing systems 2025年第3期24卷 1-30页

作者： Taufique, Zain Kanduri, Anil Miele, Antonio Rahmani, Amir Bolchini, Cristiana Dutt, Nikil Liljeberg, Pasi Health Technology University of Turku Varsinais-Suomen Turku Finland University of Turku Turku Finland DEIB Politecnico di Milano Milano Italy University of California Irvine CA United States Institute of Computer Technology Technische Universitat Wien Wien Austria Dip. Elettronica e Informazione Politecnico di Milano Milano Italy Center for Embedded Computer Systems University of California at Irvine Irvine CA United States

Run-time resource management (RTM) of multi-programmed workloads on heterogeneous multi-core platforms is challenging due to (i) fixed power budget of the device, (ii) variable performance requirements of the workloads, and (iii) unknown arrival of the applications. Existing RTM solutions lack power-performance coordination, resulting in performance degradation during power actuation or power violations during performance provisioning. Exploiting inherent error-resilience of the applications can address the performance loss incurred in power actuation, by combining run-time approximation with traditional power knobs (including Dynamic Voltage/Frequency Scaling, Task Migration, Degree of Parallelism, and CPU Quota). In this work, we present an accuracy-aware resource management framework that jointly actuates run-time approximation and traditional power knobs for efficient power-performance management of multi-programmed and multi-threaded workloads running on heterogeneous mobile platforms. Our strategy configures the accuracy of the applications at run-time to exploit accuracy-performance trade-offs, by considering system-wide power-performance dynamics. We use heuristic estimation models to jointly enforce accuracy configuration and traditional power knobs settings at run-time. We evaluated our framework on real-world embedded mobile platforms, including Odroid XU3 and Asus Tinker Edge R boards to demonstrate the efficiency of our proposed approach across multiple workload scenarios. Our approach achieved 25% lower performance violations against the state-of-the-art run-time resource management policies at the cost of 2.2% accuracy loss across six applications. © 2025 Copyright held by the owner/author(s).

关键词： and dynamic power approximation DVFS Run-time mapping

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A weakly supervised pavement crack segmentation based on adversarial learning and transformers

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Multimedia systems 2025年第3期31卷 1-21页

作者： Apedo, Yvon Tao, Huanjie School of Computer Science Northwestern Polytechnical University Xi’an People’s Republic of China Engineering and Research Center of Embedded Systems Integration (Northwestern Polytechnical University) Ministry of Education Xi’an People’s Republic of China National Engineering Laboratory for Integrated Aero-Space-Ground-Ocean Big Data Application Technology Xi’an People’s Republic of China

While pixel-level crack segmentation has demonstrated significant potential in infrastructure inspections, its reliance on detailed annotations poses challenges for widespread adoption due to the time-consuming and expensive nature of such labeling. In response, weakly supervised crack segmentation has garnered attention as it eliminates the need for pixel-level annotations. However, existing methods, primarily based on class activation maps (CAM), involve complex training processes and suffer from poor performance due to misalignment between CAM-generated labels and the true target in the image. To address these challenges, we propose a weakly supervised approach for crack segmentation that simultaneously generates synthetic crack images and performs segmentation through adversarial learning. Unlike traditional methods that rely on coarse labels, our approach leverages synthetic crack images with corresponding labels, effectively eliminating issues of misalignment and noisy pseudo-labels. Our method introduces an encoder-decoder architecture for the segmentation model, incorporating a Transformer-based Feature Enhancement module (TFE) in the encoder. This module is specifically designed to capture long-range dependencies and efficiently integrate both high- and low-level features. Additionally, the model includes a Hilo block to extract both high- and low-frequency information from the images, along with a Progressive Shrinking Decoder (PSD) to aggregate and refine adjacent feature maps. Extensive experiments were conducted, and our model achieved an ODS of 67.12% on the CrackForest dataset, 60.11% on the Crack500 dataset, and 44.80% on the AEL dataset. These results demonstrate that our model outperforms several existing weakly supervised pavement segmentation methods across these datasets.

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An evaluation framework for energy aware buildings using statistical model checking

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Science China(Information Sciences) 2012年第12期55卷 2694-2707页

作者： DAVID Alexandre LARSEN Kim G. MIKUIONIS Marius SKOU Arne Center for Embedded Software Systems Department of Computer ScienceAalborg University

Cyber-physical systems are to be found in numerous applications throughout *** principal barrier to develop trustworthy cyber-physical systems is the lack of expressive modelling and specification formalisms supported by efficient tools and *** overcome this barrier,we extend in this paper the modelling formalism of the tool UPPAAL-SMC to stochastic hybrid automata,thus providing the expressive power required for modelling complex cyber-physical *** application of Statistical Model Checking provides a highly scalable technique for analyzing performance properties of this formalisms.A particular kind of cyber-physical systems are Smart Grids which together with Intelligent,Energy Aware Buildings will play a major role in achieving an energy efficient society of the *** this paper we present a framework in UPPAAL-SMC for energy aware buildings allowing to evaluate the performance of proposed control strategies in terms of their induced comfort and energy profiles under varying environmental settings(***,user behavior etc.).To demonstrate the intended use and usefulness of our framework,we present an application to the Hybrid systems Verification Benchmark.

关键词： timed automata stochastic hybrid systems model checking statistical model checking performance evaluation energy consumption cyber physical systems smart grid energy aware buildings

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Adaptively Aggregating Pyramid Spatial-temporal Feature for Video Person Re-Identification 25

Adaptively Aggregating Pyramid Spatial-temporal Feature for ...

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Proceedings of the 4th International Conference on computer, Artificial Intelligence and Control Engineering

作者： Zhong Han Qianyue Duan Jianfeng An Huanjie Tao Yangzhou Collaborative Innovation Research Institute of Shenyang Aircraft Design and Research Institute Co. Ltd Yangzhou Jiangsu China School of Computer Science Northwestern Polytechnical University Xi' an Shaanxi China School of Computer Science Northwestern Polytechnical University Xi' an Shaanxi China Engineering and Research Center of Embedded Systems Integration (Northwestern Polytechnical University) Ministry of Education Xi' an Shaanxi China

ISBN: (纸本)9798400712647

Video person re-identification (ReID) aims to identify a particular person from the non-overlapping camera views by matching video sequences. It is challenging due to many complex factors, such as similar appearance, occlusion, pose, and viewpoint variation. Pyramid spatial-temporal aggregation (PSTA) is an important method that addresses these challenges. However, PSTA adopts a simple feature addition operation to fuse the hierarchical feature vectors into the video-level representations for video person ReID, which may cause the discriminative information in the feature vectors to be diluted. To solve the above issue, this paper presents an adaptive pyramid spatial-temporal aggregation network (APSNet) to learn more discriminative features. In APSNet, an adaptive feature fusion module (AFFM) is designed to adaptively recalibrate the channel feature responses by explicitly modeling the interdependence between channels. The designed AFFM can enhance the useful features and suppress the interference features during the feature fusion stage, resulting in more discriminative video-level feature representations. Experimental results demonstrate that APSNet has a better performance than PSTA on the MARS dataset, which reaches 86.2% mAP accuracy and 91.2% Rank-1 accuracy. Our APSNet improves the mAP accuracy by 0.4% compared with PSTA.

关键词： Attention Mechanism

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Rapture of the deep

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IEEE Spectrum 2010年第2期47卷 40-41页

作者： Weiss, Giselle Center for Embedded Computer Systems University of California Irvine USA

He makes the dive computer that every aquanaut wants. On one of the last shimmering days of summer, two weathered, middleaged men undress in a parking lot on the northeastern shore of Lake Zurich. This is the city's Gold Coast, where a halfway decent villa will set you back a couple of million francs. Jabbering in a Swiss dialect while working with swift, sure hands, the divers pull on thick black exposure suits and 20 kilograms of gear, including two big steel cylinders of pressurized breathing gas. © 2006 IEEE.

关键词： Lakes Wrist computer aided manufacturing Fellows Hair Chirp Testing Safety Underwater equipment Job shop scheduling

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Energy-efficient design for highly associative instruction caches in next-generation embedded processors

Energy-efficient design for highly associative instruction c...

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Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04

作者： Aragon, Juan Luis Nicolaescu, Dan Veidenbaum, Alex Badulescu, Ana-Maria Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)0769520855

This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructions in a given I-cache fetch are used due to branches. The proposed predictor determines which instructions in a cache access will be used and does not fetch any other instructions. Results show an average I-cache energy savings of 44% over the baseline case and 6% over the segmented case with no negative impact on performance.

关键词： Microprocessor chips

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A simplified java bytecode compilation system for resource-constrained embedded processors

A simplified java bytecode compilation system for resource-c...

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CASES'07: 2007 International Conference on Compilers, Architecture, and Synthesis for embedded systems

作者： Badea, Carmen Nicolau, Alexandru Veidenbaum, Alexander V. Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)9781595938268

embedded platforms are resource-constrained systems in whichperformance and memory requirements of executed code are ofcritical importance. However, standard techniques such as full just-in-time(JIT) compilation and/or adaptive optimization (AO) may not be appropriate for this type of systems due to memory and compilation overheads. The research presented in this paper proposes a technique that combines some of the main benefits of JIT compilation, superoperators(SOs) and profile-guided optimization, in order to deliver a lightweight Java bytecode compilation system, targeted for resource-constrained environments, that achieves runtime performance similar to that of state-of-the-art JIT/AO systems, while having a minimal impact on runtime memory *** key ideas are to use profiler-selected, extended bytecode basic blocks as superoperators (new bytecode instructions) and to perform few, but very targeted, JIT/AO-like optimizations at compile time only on the superoperators. bytecode, as directed by compilation .hints. encoded as annotations. As such, our system achieves competitive performance to a JIT/AO system, but witha much lower impact on runtime memory consumption. Moreover,it is shown that our proposed system can further improveprogram performance by selectively inlining method calls embedded in the chosen superoperators, as directed by runtime profiling data and with minimal impact on classfile size. For experimental evaluation, we developed three Virtual Machines(VMs) that employ the ideas presented above. The customized VMs are first compared (w.r.t. runtime performance) to a simple, fast-to-develop VM (baseline) and then to a VM that employs JIT/AO. Our best-performing system attains speedups ranging from a factor of 1.52 to a factor of 3.07, w.r.t. to the baseline VM. When compared to a state-of-the-art JIT/AO VM, our proposed system performs better for three of the benchmarks and worse by less than a factor of 2 for three others. But our SO-ext

关键词： embedded systems

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Generic netlist representation for system and PE level design exploration

Generic netlist representation for system and PE level desig...

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CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Gorjiara, Bita Reshadi, Mehrdad Chandraiah, Pramod Gajski, Daniel Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)1595933700

Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems require more productive design approaches starting from high-level languages such as C. On the other hand, tight constraints of embedded systems require careful design exploration at system level (coarse grained exploration) and at the processing-element (PE) level (fine grained exploration).In this paper we presented GNR, a formal modeling approach, developed to improve productivity of designing systems and processing elements, the same way that traditional ADLs improved productivity for designing processors. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. Using relatively short GNR description, we explored several designs for implementing an MP3 decoder and achieved 3.25 speedup compared to MicroBlaze processor. We have also developed a web-based interface for our tools, so that users can upload and evaluate new architectures described in GNR. Our toolset and GNR is an intermediate step towards synthesis of TLM to RTL. © Copyright 2006 ACM.

关键词： systems analysis

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Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs

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ACM Transactions on Reconfigurable Technology and systems 2008年第2期1卷 1-21页

作者： Gorjiara, Bita Reshadi, Mehrdad Gajski, Daniel Center for Embedded Computer Systems University of California at Irvine United States

Horizontal Microcoded Architecture (HMA) is a paradigm for designing programmable highperformance processing elements (PEs). However, it suffers from large code size, which can be addressed by compression. In this article, we study the code size of one of the new HMA-based technologies called No-Instruction-Set computer (NISC). We show that NISC code size can be several times larger than a typical RISC processor, and we propose several low-overhead dictionarybased code compression techniques to reduce its code size. Our compression algorithm leverages the knowledge of “don't care” values in the control words and can reduce the code size by 3.3 times, on average. Despite such good results, as shown in this article, these compression techniques lead to poor FPGA implementations because they require many on-chip RAMs. To address this issue, we introduce an FPGA-aware dictionary-based technique that uses the dual-port feature of on-chip RAMs to reduce the number of utilized block RAMs by half. Additionally, we propose cascading two-levels of dictionaries for code size and block RAM reduction of large programs. For an MP3 application, a merged, cascaded, three-dictionary implementation reduces the number of utilized block RAMs by 4.3 times (76%) compared to a NISC without compression. This corresponds to 20% additional savings over the best single level dictionary-based compression. © 2008, ACM. All rights reserved.

关键词： Algorithms Design dictionary based compression Experimentation FPGA memory optimization Microcoded architectures no-instruction-set computer Performance

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Pointer re-coding for creating definitive MPSoC models

Pointer re-coding for creating definitive MPSoC models

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CODES+ISSS 2007: 5th International Conference on Hardware/Software Codesign and System Synthesis

作者： Chandraiah, Pramod Dömer, Rainer Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)9781595938244

Today's MPSoC synthesis and exploration design flows start from an abstract input specification model captured in a system level design language. Usually this model is created from a C reference code by encapsulating the computation and the communication using behaviors and channels. However, often pointers in the reference code hamper the necessary analysis and transformations. In this paper, we present an automated approach to re-code and eliminate pointers. By re-coding the pointer accesses to the actual variables, MPSoC models with definitive computational blocks that communicate using explicit channels become possible. Our pointer re-coding approach not only increases synthesizeability, analyzeability and verifiability by system tools, but also helps the designer in program comprehension. Our experiments show that this approach is not only feasible, but also effective in creating better models of real-life applications in shorter time. Copyright 2007 ACM.

关键词： Encoding (symbols)

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