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2007 International Conference on Design and Technology of Integrated systems in Nanoscale Era, DTIS 2007

作者： Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine United States Center for Embedded Computer Systems University of Illinois Urbana-Champaign United States UCI

ISBN: (纸本)1424412781

With complexities of systems-on-Chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a SOC out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure. In order to find the solution, we will look first at the system gap between SW and HW designs and derive requirements for the system design flow that includes software as well as hardware. In order to enable new tools for model generation, simulation, synthesis and verification, the design flow has to be well defined with unique abstraction levels, model semantics and model transformations that correspond to design decisions made by designers. We will introduce the concept of model algebra that supports this approach and can serve as un enabler for the extreme makeover of system design and, consequently, system industry. We will support this concept with hard data and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of billion-transistor systems to the basic principles of design science only. © 2007 IEEE.

关键词： System-on-chip

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Access Pattern-Based Memory and Connectivity Architecture Exploration

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ACM Transactions on embedded Computing systems 2003年第1期2卷 33-73页

作者： Grun, Peter Dutt, Nikil Nicolau, Alex Center for Embedded Computer Systems University of California Irvine CA United States

Memory accesses represent a major bottleneck in embedded systems power and performance. Traditionally, designers tried to alleviate this problem by relying on a simple cache hierarchy, or a limited use of special purpose memory modules such as stream buffers. Although real-life applications contain a large number of memory references to a diverse set of data structures, a significant percentage of all memory accesses in the application are generated from a few memory instructions that exhibit predictable, well-known access patterns;this creates an opportunity for memory customization, targeting the needs of these access patterns. We present APEX, an approach that extracts, analyzes and clusters the most active access patterns in the application, and aggressively customizes the memory architecture to match the needs of the application. Moreover, though the memory modules are important, the rate at which the memory system can produce the data for the CPU is significantly impacted by the connectivity architecture between the memory subsystem and the CPU. Thus, it is critical to consider the connectivity architecture early in the design flow, in conjunction with the memory architecture. We couple the exploration of memory modules together with their connectivity, to evaluate a wide range of cost, performance, and energy connectivity architectures. We use a heuristic to prune the design space, guiding the exploration towards the most promising designs. We present experiments on a set of large real-life benchmarks, showing significant performance improvements for varied cost and power characteristics, allowing the designer to evaluate customized memory and connectivity configurations for embedded systems. © 2003, ACM. All rights reserved.

关键词： access patterns architecture exploration Design Experimentation Memory Performance

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System-level power-performance trade-offs in bus matrix communication architecture synthesis

System-level power-performance trade-offs in bus matrix comm...

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CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Pasricha, Sudeep Park, Young-Hwan Kurdahi, Fadi J. Dutt, Nikil Center for Embedded Computer Systems University of California Irvine CA

ISBN: (纸本)1595933700

System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multi-processor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power-performance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro-models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macro-models incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach. © Copyright 2006 ACM.

关键词： Communication systems

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Fuzzy logic based adaptive hierarchical scheduling for periodic real-time tasks 5

Fuzzy logic based adaptive hierarchical scheduling for perio...

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5th embedded Operating System Workshop - Embed With Linux 2015, EWiLi 2015

作者： Springer, Tom Peter, Steffen Givargis, Tony Center for Embedded Computer Systems University of California Irvine United States

In this paper, we present a new scheduling approach for real-time tasks in an embedded system. Our method utilizes hierarchical scheduling to provide a resource based allocation scheme while using a fuzzy logic based feedback scheduler to react to environmental changes within the application. The primary goal is to provide a scheduling mechanism that can adapt to overload conditions but still present a level of service while enforcing the temporal isolation between independent applications. The scheduler then considers this level of service to make scheduling decisions based upon a task's service requirements, such as criticality or timeliness. Implemented in Vx Works on a uniprocessor-based platform results show that our adaptive approach provides significant advantages, during overload conditions, over traditional fixed-priority scheduling schemes.

关键词： Real time systems

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System design extreme makeover

System design extreme makeover

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28th International Convention Proceedings: Microelectronics, Electronics and Electronic Technologies MEET, Hypermedia and Grid systems HGS 2OO5

作者： Gajski, Daniel D. Center for Embedded Computer Systems University of California at Irvine United States

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Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis 13

Designer-in-the-loop recoding of ESL models using static par...

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16th International Workshop on Software and Compilers for embedded systems, M-SCOPES 2013

作者： Han, Xu Chen, Weiwei Domer, Rainer Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781450321426

At the Electronic System Level (ESL), a well-defined design model enables early design space exploration and automatic synthesis on custom multiprocessor platforms. However, the initial design model is usually manually recoded from unstructured and sequential source code. To efficiently create cleanly structured and parallel models, this paper proposes a designer-in-the-loop approach on Eclipse platform where the system model is analyzed and recoded using automated functions. Particularly, advanced static analysis at compile time can guarantee that the parallelism in the model is safe and free from race conditions. Experiments using the tool with a class of graduate students show significant productivity gains and error reduction in model creation. Copyright © 2013 ACM.

关键词： Productivity

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Deterministic service guarantees for NAND flash using partial block cleaning 08

Deterministic service guarantees for NAND flash using partia...

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embedded systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

作者： Choudhuri, Siddharth Givargis, Tony Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781605584706

NAND flash idiosyncrasies such as bulk erase and wear leveling results in non-linear and unpredictable read/write access times. In case of application domains such as streaming multimedia and real-time systems, a deterministic read/write access time is desired during design time. We propose a novel NAND flash translation layer called GFTL that guarantees fixed upper bounds (i.e., worst case service rates) for reads and writes that are comparable to a theoretical ideal case. Such guarantees are made possible by eliminating sources of non-determinism in GFTL design and using partial block cleaning. GFTL performs garbage collection in partial steps by dividing the garbage collection of a single block into several chunks, thereby interleaving and hiding the garbage collection latency while servicing requests. Further, GFTL guarantees are independent of flash utilization, size or state. Along with theoretical bounds, benchmark results show the efficacy of our approach. Based on our experiments, GFTL requires an additional 16% of total blocks for flash management. GFTL service guarantees can be calculated from flash specifications. Thus, with GFTL, a designer can determine the service guarantees and size requirements apriori, during design time. Copyright 2008 ACM.

关键词： Real time systems

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PoliMakE: A policy making engine for secure embedded software execution on chip-multiprocessors

PoliMakE: A policy making engine for secure embedded softwar...

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5th Workshop on embedded systems Security, WESS '10

作者： Bathen, Luis Angel D. Dutt, Nikil Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781450300780

Secure software execution on chip-multiprocessor platforms is compromised by threats such as software-based side channel attacks that expose information from shared memory. The increasing amount of shared (memory or computational) resources on emerging chip-multiprocessors further exacerbates security threats, highlighting the need for secure policies to manage on-chip resources. We present PoliMakE, a methodology that enables exploration and generation of customized policies to guarantee secure software execution on a chip-multiprocessor system in the presence of software-based side channel attacks. PoliMakE analyzes an application's security needs and generates a series of custom policies that dictate how to safely execute tasks and efficiently manage the computational, communication, and memory resources. Our experimental results on DRM, JPEG as well as some synthetic applications show that PoliMakE enables secure software execution with minimal performance overhead, while reducing power consumption, since the policies are customized to efficiently utilize the available on-chip resources. For the case study of running DRM in secure mode concurrently with JPEG encoding, we are able to observe 61% performance improvement when compared to standard approaches. Our policy generation engine is able to generate policies in only a matter of minutes for secure applications with hundreds of tasks. Unsecure applications were observed to resume execution up to 99% faster than with the traditional halt approach. © 2010 ACM.

关键词： Engines

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Automatic generation of Hardware dependent Software for MPSoCs from abstract system specifications

Automatic generation of Hardware dependent Software for MPSo...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Schirner, Gunar Gerstlauer, Andreas Dömer, Rainer Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781424419227

Increasing software content in embedded systems and SoCs drives the demand to automatically synthesize software binaries from abstract models. This is especially critical for Hardware dependent Software (HdS) due to the tight coupling. In this paper, we present our approach to automatically synthesize HdS from an abstract system model. We synthesize driver code, interrupt handlers and startup code. We furthermore automatically adjust the application to use RTOS services. We target traditional RTOS-based multi-tasking solutions, as well as a pure interrupt-based implementation (without any RTO S ). Our experimental results show the automatic generation of final binary images for six real-life target applications and demonstrate significant productivity gains due to automation. Our HdS synthesis is an enabler for efficient MPSoC development and rapid design space exploration. ©2008 IEEE.

关键词： Binary images

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Performance improvement of block based NAND flash translation layer

Performance improvement of block based NAND flash translatio...

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CODES+ISSS 2007: 5th International Conference on Hardware/Software Codesign and System Synthesis

作者： Choudhuri, Siddharth Givargis, Tony Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781595938244

With growing capacities of flash memories, an efficient layer to manage read and write access to flash is required. NFTL is a widely used block based flash translation layer designed to manage NAND flash memories. NFTL is designed to achieve fast write times at the expense of slower read times. While traditionally, it is assumed that the read traffic to secondary storage is insignificant, as reads are cached, we show that this need not be true for NAND flash based storage due to garbage collection and reclamation processes. In this work, we present two independent techniques that extend NFTL and improve the read throughput in particular. The techniques presented add a minimal amount of RAM overhead to a flash controller, while providing, on an average, a 22.9% improvement in page read times and a 2.6% improvements in page write times on a set of file system and rigorous synthetic benchmarks. The techniques presented are well suited for flash controllers that are typically space constrained and have minimal processing power. Copyright 2007 ACM.

关键词： Flash memory

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