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2014 Workshop on Embed With Linux, EWiLi 2014

作者： Springer, Tom Peter, Steffen Givargis, Tony Center for Embedded Computer Systems University of California Irvine United States

In this paper we outline the Adaptive Resource Allocation Protocol (ARAP) as an improved resource synchronization algorithm for hierarchically scheduled real-time systems. ARAP exploits knowledge about task utilization, using a proportional integral-derivative (PID) controller, to estimate required resource bandwidth and improve scheduling decisions. Our analysis and experiments with RTSIM show that ARAP provides better temporal isolation and resource utilization during periods of transient overload compared to state-of-the-art resource synchronization algorithms. Implemented as part of VxWorks, the results are confirmed using an avionic system, for which ARAP substantially reduced the number of hard real-time deadline misses.

关键词： Real time systems

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Automatic generation of Hardware dependent Software for MPSoCs from abstract system specifications

Automatic generation of Hardware dependent Software for MPSo...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Schirner, Gunar Gerstlauer, Andreas Dömer, Rainer Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781424419227

Increasing software content in embedded systems and SoCs drives the demand to automatically synthesize software binaries from abstract models. This is especially critical for Hardware dependent Software (HdS) due to the tight coupling. In this paper, we present our approach to automatically synthesize HdS from an abstract system model. We synthesize driver code, interrupt handlers and startup code. We furthermore automatically adjust the application to use RTOS services. We target traditional RTOS-based multi-tasking solutions, as well as a pure interrupt-based implementation (without any RTO S ). Our experimental results show the automatic generation of final binary images for six real-life target applications and demonstrate significant productivity gains due to automation. Our HdS synthesis is an enabler for efficient MPSoC development and rapid design space exploration. ©2008 IEEE.

关键词： Binary images

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Rappit: Framework for synthesis of host-assisted scripting engines for adaptive embedded systems

Rappit: Framework for synthesis of host-assisted scripting e...

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3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and systems Synthesis CODES+ISSS 2005

作者： Hahn, Jiwon Xie, Qiang Chou, Pai H. Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)1595931619

Scripting is a powerful, high-level, cross-platform, dynamic, easy way of composing software modules as black boxes. Unfortunately, the high runtime overhead has prevented scripting from being widely adopted in embedded applications. This work proposes to overcome these obstacles by synthesizing light-weight, host-assisted scripting engines for embedded systems. The result is dramatically shortened development cycle due to the much higher-level abstraction, interactive access and dynamic reconfigurability, robust in-field software upgradability, and compact code size. This framework has been successfully applied to ultra low-power sensor nodes with under 10KB of program memory to high-performance platforms with fast Ethernet. Copyright 2005 ACM.

关键词： embedded systems

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Pushing the throughput limit of low-complexity wireless embedded sensing systems

Pushing the throughput limit of low-complexity wireless embe...

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IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing

作者： Salmani, Vahid Chou, Pai H. Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9780769540498

To maximize the communication throughput for wireless sensing systems, designers have attempted various combinations of protocol design and manual code optimization. Although the theoretical bandwidth limit is easy to determine loosely, there have been no systematic ways to arrive at a tight upper-bound. One contribution of this paper is a formula for deriving a tight upper-bound on the throughput of low-complexity wireless interfaces transmitting packets of a fixed size. It takes into account not only the software execution times on the nodes but also other communication protocols that must be bridged by the base station. The proposed upper-bound, which we believe is the tightest, represents the maximum amount of bandwidth utilization that can be achieved in practice. It can also serve as a means of comparing protocols built on different platforms. Another contribution is a streamlined schedule-based protocol, called RIPE-MAC, which achieves at least 83% of the upper-bound, significantly higher than previously achieved throughput. The proposed protocol needs no clock synchronization and incurs no further complexity on sensor nodes. In the proposed protocol, synchronization and schedule updates are reduced to a single pull message. © 2010 IEEE.

关键词： Time division multiple access

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Equivalence Checking of Arithmetic Expressions using Fast Evaluation

Equivalence Checking of Arithmetic Expressions using Fast Ev...

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CASES 2005: International Conference on Compilers, Architecture, and Synthesis for embedded systems

作者： Ghodrat, Mohammad Ali Givargis, Tony Nicolau, Alex Department of Computer Science Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)159593149X

Arithmetic expressions are the fundamental building blocks of hardware and software systems. An important problem in computational theory is to decide if two arithmetic expressions are equivalent. However, the general problem of equivalence checking, in digital computers, belongs to the NP Hard class of problems. Moreover, existing general techniques for solving this decision problem are applicable to very simple expressions and impractical when applied to more complex expressions found in programs written in high-level languages. In this paper we propose a method for solving;the arithmetic expression equivalence problem using partial evaluation. In particular, our technique is specifically designed to solve the problem of equivalence checking of arithmetic expressions obtained from high-level language descriptions of hardware/software systems, which consists of regular arithmetic operators (+, -, x) and logical operators (and, or, not). In our method, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Our results show that the proposed method is fast enough to be of use in practice. Copyright 2005 ACM.

关键词： Digital arithmetic

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Modeling and Validation of Pipeline Specifications

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ACM Transactions on embedded Computing systems 2004年第1期3卷 114-139页

作者： Mishra, Prabhat Dutt, Nikil Center for Embedded Computer Systems 444 Computer Science University of California Irvine CA 92697-3430 United States

Verification is one of the most complex and expensive tasks in the current systems-on-Chip design process. Many existing approaches employ a bottom-up approach to pipeline validation, where the functionality of an existing pipelined processor is, in essence, reverse-engineered from its RT-level implementation. Our validation technique is complementary to these bottom-up approaches. Our approach leverages the system architect's knowledge about the behavior of the pipelined architecture, through architecture description language (ADL) constructs, and thus allows a powerful top-down approach to pipeline validation. The most important requirement in top-down validation process is to ensure that the specification (reference model) is golden. This paper addresses automatic validation of processor, memory, and coprocessor pipelines described in an ADL. We present a graph-based modeling that captures both structure and behavior of the architecture. Based on this model, we present algorithms to ensure that the static behavior of the pipeline is well formed by analyzing the structural aspects of the *** applied our methodology to verify specification of several realistic architectures from different architectural domains to demonstrate the usefulness of our approach. © 2004, ACM. All rights reserved.

关键词： Algorithms architecture description language Design Languages Modeling of processor pipeline pipeline validation pipelined processor specification Verification

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Highly-cited ideas in system codesign and synthesis 08

Highly-cited ideas in system codesign and synthesis

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embedded systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

作者： Vahid, Frank Givargis, Tony Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems UC Irvine United States Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781605584706

We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/software codesign and system synthesis community. Citations, meaning non-self-citations only, were considered from all papers known to Google Scholar, as well as only from subsequent CODES/ISSS papers. We list the most-cited CODES/ISSS papers of each year, summarizing their topics, and discussing common features of those papers. For comparison purposes, we also measured citations for the computer architecture community's ISCA and MICRO conferences, and for the field-programmable gate array community's FPGA and FCCM conferences. We point out several interesting differences among the citation patterns of the three communities. Copyright 2008 ACM.

关键词： computer architecture

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FlashBox: A system for logging non-deterministic events in deployed embedded systems 09

FlashBox: A system for logging non-deterministic events in d...

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24th Annual ACM Symposium on Applied Computing, SAC 2009

作者： Choudhuri, Siddharth Givargis, Tony Center for Embedded Computer Systems University of California Irvine CA United States

ISBN: (纸本)9781605581668

The ability to postmortem failures in deployed systems due to non-deterministic events is useful in crash investigations. With this goal in mind, we propose FlashBox - a system that acts as a black box for embedded systems, recording non-deterministic events (interrupts). The FlashBox hardware consists of a microcontroller and flash memory. The FlashBox software is an extension to a compiler, enabling recording capabilities at various granularities. There are no source code modifications required to use FlashBox and no assumptions made on processor capabilities such as hardware counters. The FlashBox log can be used for faithful replay with a goal to isolate faults and reason about failure. We present a prototype implementation of FlashBox that logs non-deterministic events on an AVR ATMega169 microcontroller. The FlashBox prototype consists of a 8051 microcontroller with flash memory. The avr-gcc compiler has been extended to log non-deterministic events. Based on our experimental results, FlashBox results in 10-23% overhead while providing capability to log non-deterministic events at instruction level granularity. With decreasing cost of flash memories, FlashBox provides a low cost logging mechanism. The use of standard I/O communication protocols enhances portability, enabling ease of integration for different classes of embedded systems. Copyright 2009 ACM.

关键词： embedded systems

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Processor-Memory Coexploration Using an Architecture Description Language

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ACM Transactions on embedded Computing systems 2004年第1期3卷 140-162页

作者： Mishra, Prabhat Mamidipaka, Mahesh Dutt, Nikil Center for Embedded Computer Systems 444 Computer Science University of California Irvine CA 92697-3430 United States

Memory represents a major bottleneck in modern embedded systems in terms of cost, power, and performance. Traditionally, memory organizations for programmable embedded systems assume a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for specific target applications. However, such a processor-memory coexploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem configuration, generate a memory-aware software toolkit, and perform coexploration of the processor-memory architectures. We present a set of experiments using our memory-aware architectural description language (ADL) to drive the exploration of the memory subsystem for the TI C6211 processor architecture, demonstrating cost, performance, and energy trade-offs. © 2004, ACM. All rights reserved.

关键词： architecture description language Design design space exploration Experimentation Languages memory exploration Processor-memory codesign

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E 2: Less energy through multi-copy cache

E 2: Less energy through multi-copy cache

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6th embedded systems Week 2010, ESWEEK 2010 - 2010 International Conference on Compilers, Architecture, and Synthesis for embedded systems, CASES'10

作者： Chakraborty, Arup Homayoun, Houman Khajeh, Amin Dutt, Nikil Eltawil, Ahmed Kurdahi, Fadi Center for Embedded Computer Systems University of California Irvine CA United States

ISBN: (纸本)9781605589039

Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation-induced failures in cache SRAM arrays, which compromise cache reliability. We present Multi-Copy Cache (MC2), a new cache architecture that achieves significant reduction in energy consumption through aggressive voltage scaling, while maintaining high error resilience (reliability) by exploiting multiple copies of each data item in the cache. Unlike many previous approaches, MC2 does not require any error map characterization and therefore is responsive to changing operating conditions (e.g., Vdd-noise, temperature and leakage) of the cache. MC2 also incurs significantly lower overheads compared to other ECC-based caches. Our experimental results on embedded benchmarks demonstrate that MC2 achieves up to 60% reduction in energy and energy-delay product (EDP) with only 3.5% reduction in IPC and no appreciable area overhead.

关键词： Fault tolerance

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