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Cryptic primes

引用

IEEE Potentials 2004年第1期23卷 43-45页

作者： Kejariwal, Arun Center for Embedded Computing Systems University of California Irvine United States IEEE United States IEEE Computer Society United States

No abstract available

关键词： Public key Public key cryptography Internet Security Computational complexity Equations Transmitters

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High performance annotation-aware JVM for java cards

High performance annotation-aware JVM for java cards

引用

5th ACM International Conference on embedded Software, EMSOFT 2005

作者： Azevedo, Ana Kejariwal, Arun Veidenbaum, Alex Nicolau, Alexandra Center for Embedded Computer Systems School of Information and Computer Science University of California Irvine United States

ISBN: (纸本)1595930914

Early applications of smart cards have focused in the area of personal security. Recently, there has been an increasing demand for networked, multi-application cards. In this new scenario, enhanced application-specific on-card Java applets and complex cryptographic services are executed through the smart card Java Virtual Machine (JVM). In order to support such computation-intensive applications, contemporary smart cards are designed with built-in microprocessors and memory. As smart cards are highly area-constrained environments with memory. CPU and peripherals competing for a very small die space, the VM execution engine of choice is often a small, slow interpreter. In addition, support for multiple applications and cryptographic services demands high performance VM execution engine. The above necessitates the optimization of the JVM for Java Cards. In this paper we present the concept of an annotation-aware interpreter that optimizes the interpreted execution of Java code using Java bytecode SuperOperators (SOs). SOs are groups of bytecode operations that are executed as a specialized VM instruction. Simultaneous translation of all the bytecode operations in an SO reduces the bytecode dispatch cost and the number of stack accesses (data transfer to/from the Java operand stack) and stack pointer updates. Furthermore, SOs help improve native code quality without hindering class file portability. Annotation attributes in the class files mark the occurrences of valuable SOs, thereby dispensing the expensive task of searching and selecting SOs at runtime. Besides, our annotation-based approach incurs minimal memory overhead as opposed to just-in-time (JIT) compilers. We obtain an average speedup of 18% using an interpreter customized with the top SOs formed from operation folding patterns. Further, we show that greater speedups could be achieved by statically adding to the interpreter application-specific SOs formed by top basic blocks. The effectiveness of our approa

关键词： Java programming language

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Automatic generation of bus functional models from transaction level models

Automatic generation of bus functional models from transacti...

引用

Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004

作者： Shin, Dongwan Abdi, Samar Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine CA 92697 United States

This paper presents methodology and algorithms for generating bus functional models from transaction level models in system level design. Transaction level models are often used by designers for prototyping the bus functional architecture of the system. Being at a higher level of abstraction gives transaction level models the unique advantage of high simulation speed. This means that the designer can explore several bus functional architectures before choosing the optimal one. However, the process of converting a transaction level model to a bus functional model is not trivial. A manual conversion would not only be time consuming but also error prone. A bus functional model should also accurately represent the corresponding transaction level model. We present algorithms for automating this refinement process. Experimantal results presented using a tool based on these algorithms show their usefulness and feasibility.

关键词： computer systems

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Automatic generation of transaction level models for rapid design space exploration

Automatic generation of transaction level models for rapid d...

引用

CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Shin, Dongwan Gerstlauer, Andreas Peng, Junyu Dömer, Rainer Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine CA 92697 United States

ISBN: (纸本)1595933700

Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer's productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space. © Copyright 2006 ACM.

关键词： Logic design

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Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations 11

Reliability-aware placement in SRAM-based FPGA for voltage s...

引用

embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM International Conference on Hardware/Software-Codesign and System Synthesis, CODES+ISSS'11

作者： Golshan, Shahin Khajeh, Amin Homayoun, Houman Bozorgzadeh, Eli Eltawil, Ahmed Kurdahi, Fadi J. Center of Embedded Computer Systems University of California Irvine CA 92697 United States

ISBN: (纸本)9781450307154

With advances in technology scaling, the configuration memory in SRAM-based FPGA is contributing a large portion of power consumption. Voltage scaling has been widely used to address the increases in power consumption in submicron regimes. However, with the advent of process variation in the configuration SRAMs, voltage scaling can undermine the integrity of a design implemented on the FPGA device as the design's functionality is determined by the contents of the configuration SRAMs. In this paper, we propose to exploit the abundance of homogenous resources on FPGA, in order to realize voltage scaling in the presence of process variation. Depending on the design to be implemented on FPGA, we select the minimal voltage that sustains a reliable placement. We then introduce a novel 2-phase placement algorithm that maximizes the reliability of the implemented design when voltage scaling is applied to the configuration memory. In the first phase, pre-deployment placement, we maximize the reliability of the implemented designs considering the a priori distribution of SRAM failures due to process variation and voltage scaling. The second phase, post-deployment placement, is performed once the device is fabricated in order to determine a fault-free placement of the design for the FPGA device. Our results indicate significant leakage power reduction (more than 50%) in the configuration memory when our placement technique is combined with voltage scaling with little delay degradation. Copyright 2011 ACM.

关键词： computer aided design

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Automatic model refinement for fast architecture exploration [SoC design] 7

Automatic model refinement for fast architecture exploration...

引用

7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

作者： Peng, J. Abdi, S. Gajski, D. Center for Embedded Computer Systems University of California IrvineCA92697 United States

ISBN: (纸本)0769514413

We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An architecture model is derived from the specification through a series of well defined steps in our design methodology. Traditional architecture exploration relies on manual refinement which is painfully time consuming and error prone. The automation of the refinement process provides a useful tool to the system designer to quickly evaluate several architectures in the design space and make the optimal choice. Experiments with the tool on a system design example show the robustness and usefulness of the refinement algorithm. © 2002 IEEE.

关键词： System-on-chip

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Automatic network generation for system-on-chip communication design 05

Automatic network generation for system-on-chip communicatio...

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3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and systems Synthesis CODES+ISSS 2005

作者： Shin, Dongwan Gerstlauer, Andreas Dömer, Rainer Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine CA 92697 United States

ISBN: (纸本)1595931619

With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary. In this paper, we extend previous work on automatic communication refinement to support non-traditional, network-oriented architectures beyond a single bus. From an abstract description of the desired communication channels, the refinement tools automatically generate executable models and implementations of the system communication at various levels of abstraction. Experimental results show that significant productivity gains can be, achieved, demonstrating the effectiveness of the approach for rapid, early communication design space exploration. Copyright 2005 ACM.

关键词： Communication systems

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Efficient simulation of synthesis-oriented system level designs

Efficient simulation of synthesis-oriented system level desi...

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15th International Symposium on System Synthesis

作者： Savoiu, Nick Shukla, Sandeep K. Gupta, Rajesh K. Center for Embedded Computer Systems University of California Irvine Irvine CA United States

Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware systems have some inherent parallelism efficiently expressing it depends on whether the target usage is synthesis or simulation. For synthesis, designs are usually described with synthesis tools in mind and are therefore partitioned according to the targeted hardware units. For simulation, runtime efficiency is critical but our previous work has shown that a synthesis-oriented description is not necessarily the most efficient, especially if using multiprocessor simulators. Multiprocessor simulation requires preemptive multithreading but most current C++-based high level system description languages use cooperative multithreading to exploit parallelism to reduce overhead. We have seen that, for synthesis-oriented models, along with adding preemptive threading we need to transform the threading structure for good simulation performance. In this paper we present an algorithm for automatically applying such transformations to C++-based hardware models, ongoing work aimed at proving the equivalence between the original and transformed model, and a 62% to 76% simulation time improvement on a dual processor simulator.

关键词： systems analysis

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B#: A Battery Emulator and Power Profiling Instrument

B#: A Battery Emulator and Power Profiling Instrument

引用

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03)

作者： Chou, Pai H. Park, Chulsung Park, Jae Pham, Kien Liu, Jinfeng Center for Embedded Computer Systems University of California Irvine CA 92697-2625 United States

ISBN: (纸本)158113682X

This paper describes B# (B-sharp), a programmable power supply that emulates the behavior of a battery. It measures the current load, calls a battery simulation program to compute the voltage in real time, and controls a linear regulator to mimic the voltage output of a battery. This instrument enables validation of battery-aware power-optimization techniques with accurate, controllable, reproducible results. This instrument also supports training mode with actual batteries, and it can even be used for recording and playback of a solar power source. This design has been prototyped and tested on hand-held devices with high accuracy and fast response time.

关键词： Electric batteries

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AmbiMax: Autonomous energy harvesting platform for multi-supply wireless sensor nodes

AmbiMax: Autonomous energy harvesting platform for multi-sup...

引用

2006 3rd Annual IEEE Communications Society on Sensor and Ad hoc Communications and Networks, Secon 2006

作者： Park, Chulsung Chou, Pai H. Center for Embedded Computer Systems University of California Irvine CA 92697-2625 United States

ISBN: (纸本)1424406269

AmbiMax is an energy harvesting circuit and a supercapacitor based energy storage system for wireless sensor nodes (WSN). Previous WSNs attempt to harvest energy from various sources, and some also use supercapacitors instead of batteries to address the battery aging problem. However, they either waste much available energy due to impedance mismatch, or they require active digital control that incurs overhead, or they work with only one specific type of source. AmbiMax addresses these problems by first performing maximum power point tracking (MPPT) autonomously, and then charges supercapacitors at maximum efficiency. Furthermore, AmbiMax is modular and enables composition of multiple energy harvesting sources including solar, wind, thermal, and vibration, each with a different optimal size. Experimental results on a real WSN platform, Eco, show that AmbiMax successfully manages multiple power sources simultaneously and autonomously at several times the efficiency of the current state-of-the-art for WSNs. © 2006 IEEE.

关键词： Wireless sensor networks

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