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Design, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000

作者： Halambe, Ashok Cornea, Radu Grun, Peter Dutt, Nikil Nicolau, Alex Laboratory Center for Embedded Computer Systems University of California Irvine CA 92697-3425 United States

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Verified Model Checking for Conjunctive Positive Logic

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SN computer Science 2021年第5期2卷 1-24页

作者： Abuin, Alex de Cerio, Unai Diaz Hermo, Montserrat Lucio, Paqui Computer Languages and Systems University of the Basque Country San Sebastián Spain Dependable Embedded Systems Ikerlan Research Center Mondragón Spain

We formalize, in the Dafny language and verifier, a proof system PS for deciding the model checking problem of the fragment of first-order logic, denoted FO(∀ , ∃ , ∧) , known as conjunctive positive logic (CPL). We mechanize the proofs of soundness and completeness of PS ensuring its correctness. Our formalization is representative of how various popular verification systems can be used to verify the correctness of rule-based formal systems on the basis of the least fixpoint semantics. Further, exploiting Dafny’s automatic code generation, from the completeness proof we achieve a mechanically verified prototype implementation of a proof search mechanism that is a model checker for CPL. The model checking problem of FO(∀ , ∃ , ∧) is equivalent to the quantified constraint satisfaction problem (QCSP), and it is PSPACE-complete. The formalized proof system decides the general QCSP and it can be applied to arbitrary formulae of CPL. © 2021, The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd. part of Springer Nature.

关键词： Conjunctive positive logic Dafny Model checking Proof system Quantified constraint satisfaction problem Verification

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RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions 12

RTGEN: An Algorithm for Automatic Generation of Reservation ...

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12th International Symposium on System Synthesis, ISSS 1999

作者： Grun, Peter Halambi, Ashok Dutt, Nikil Nicolau, Alex Laboratory Center for Embedded Computer Systems University of California IrvineCA92697-3425 United States

ISBN: (纸本)076950356X

Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error-prone. Furthermore, manual specification of such conflict information is infeasible for supporting rapid architectural exploration. In this paper we present an algorithm to automatically generate RTs from a high-level processor description, with the goal of avoiding manual specification of RTs, resulting in more concise architectural specifications and also supporting faster turn-around time in Design Space Exploration. We demonstrate the utility of our approach on a set of experiments using the TI C6201 VLIW DSP and DLX processor architectures, and a suite of multimedia and scientific applications.

关键词： Specifications

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The Tellez-Molina-Villa algorithm

The Tellez-Molina-Villa algorithm

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2012 Annual Meeting of the North American Fuzzy Information Processing Society, NAFIPS 2012

作者： Tellez-Velazquez, Arturo Molina-Lozano, Heron Villa-Vargas, Luis A. Microtechnology and Embedded Systems Laboratory Computer Research Center National Polytechnics Institute Mexico City Mexico

ISBN: (纸本)9781467323376

The Tellez-Molina-Villa (TMV) algorithm is a new defuzzification method for interval type-2 fuzzy systems. It is based on found the mean trajectory of any interval type-2 fuzzy set. With the mean trajectory we pretend to find the type-1 reduced fuzzy set of the interval type-2 fuzzy set. With this algorithm we try to find the generalized centroid of any interval type-2 fuzzy set. Also, we try to increase the type-2 fuzzy logic system accuracy. In general we found from 5 defuzzification methods that try to extract a crisp value from an interval type-2 fuzzy set as a representative value. First is necessary to obtain a type-1 fuzzy set from the type-2 fuzzy set, second from this reduced fuzzy set obtain a single crisp value. This crisp value representsa lot of information, so that is necessary to do these steps carefully because we can obtain misinformation from the type-2 fuzzy inference system. In this paper we present some result from the new algorithm, and in order to compare the TMV algorithm we present comparative results with 5 type-2 defuzzification methods. From the obtained results we demonstrated that the TMV approach performs better that the Nie-Tan method. In fact, we can say that the TMV algorithm has at least equivalent results than Karnik-Mendel algorithm that in our opinion is one of the best defuzzification methods, but with the difference that the TMV algorithm is based on the mean trajectory of an interval type-2 fuzz set. © 2012 IEEE.

关键词： Fuzzy sets

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computer-aided recoding to create structured and analyzable system models

Computer-aided recoding to create structured and analyzable ...

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作者： Chandraiah, Pramod Dömer, Rainer Center for Embedded Computer Systems University of California at Irvine Irvine CA 92697-2625 United States

In embedded system design, the quality of the input model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-written system model, tools today are effective in generating working implementations. However, readily available C reference code is not conducive for immediate system synthesis as it lacks needed features for automatic analysis and synthesis. Among others, the lack of proper structure and the presence of intractable pointers in the reference code are factors that seriously hamper the effectiveness of system design tools. To overcome these deficiencies, we aim to automate the conversion of flat C code into a well-structured system model by applying automated source code transformations. We present a set of computer-aided recoding operations that enable the system designer to mitigate pointer problems and quickly create the necessary structural hierarchy so that the design model becomes easily analyzable and synthesizable. Utilizing the designer's knowledge, our interactive recoding transformations aid the designer in efficiently creating well-structured system models for rapid design space exploration and successful synthesis. Our estimated and measured experimental results show significant productivity gains through a substantial reduction of the model creation time. © 2012 ACM.

关键词： embedded systems

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System-level abstraction semantics

System-level abstraction semantics

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15th International Symposium on System Synthesis

作者： Gerstlauer, Andreas Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine Irvine CA 92697-3425 United States

Raising the level of abstraction is widely seen as the solution for closing the productivity gap in system design. They key for the success of this approach, however, are well-defined abstraction levels and models. In this paper, we present such system level semantics to cover the system design process. We define properties and features of each model. Formalization of the flow enables design automation for synthesis and verification to achieve the required productivity gains. Through customization, the semantics allow creation of specific design methodologies. We applied the concepts to system languages SystemC and SpecC. Using the example of a JPEG encoder, we will demonstrate the feasibility and effectiveness of the approach.

关键词： systems analysis

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EmPro: An environment/energy emulation and profiling platform for wireless sensor networks

EmPro: An environment/energy emulation and profiling platfor...

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2006 3rd Annual IEEE Communications Society on Sensor and Ad hoc Communications and Networks, Secon 2006

作者： Park, Chulsung Chou, Pai H. Center for Embedded Computer Systems University of California Irvine Irvine CA 92697-2625 United States

ISBN: (纸本)1424406269

Quantitative evaluation of wireless sensor platforms is difficult. Unlike general purpose computers that can run SPEC benchmarks from a file, it is difficult to reproduce the environmental input needed to stimulate the sensor nodes. Even if possible, open-loop playback would be unable to correctly account for adaptivity built into the behavior of these nodes. As a result, researchers resort to simulations, which do not consider all relevant factors without significant speed penalty. To address this problem, we propose EmPro, an environment/energy emulation and profiling system for WSNs. It accurately outputs electrical signals to emulate not only digital and analog inputs to the sensors but also the power sources as well as RF attenuation according to pre-programmed sequences. This emulation approach enables researchers to run the networked sensors in real-time in a realistic manner with full controllability and reproducibility. EmPro in profiling mode can also capture the observable behavior of WSNs for detailed analysis. Experimental results on the Eco and MICA2 WSN platforms show that EmPro can drive these hardware systems in real-time with high accuracy. We expect EmPro will expedite testing and serve as a sorely needed standard benchmarking tool for WSN platforms. © 2006 IEEE.

关键词： Wireless sensor networks

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Tiny Instruction Caches For Low Power embedded systems

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ACM Transactions on embedded Computing systems 2003年第4期2卷 449-481页

作者： Gordon-Ross, Ann Cotterell, Susan Vahid, Frank Department of Computer Science University of California Riverside CA 92521 United States Center for Embedded Computer Systems at University of California Irvine United States

Instruction caches have traditionally been used to improve software performance. Recently, several tiny instruction cache designs, including filter caches and dynamic loop caches, have been proposed to instead reduce software power. We propose several new tiny instruction cache designs, including preloaded loop caches, and one-level and two-level hybrid dynamic/preloaded loop caches. We evaluate the existing and proposed designs on embedded system software benchmarks from both the Powerstone and MediaBench suites, on two different processor architectures, for a variety of different technologies. We show on average that filter caching achieves the best instruction fetch energy reductions of 60-80%, but at the cost of about 20% performance degradation, which could also affect overall energy *** show that dynamic loop caching gives good instruction fetch energy savings of about 30%, but that if a designer is able to profile a program, preloaded loop caching can more than double the savings. We describe automated methods for quickly determining the best loop cache configuration, methods useful in a core-based design flow. © 2003, ACM. All rights reserved.

关键词： architecture tuning Design embedded systems filter cache fixed program instruction cache Loop cache low energy low power

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Energy aware task scheduling with task synchronization for embedded real time systems

Energy aware task scheduling with task synchronization for e...

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2002 International Conference on Compilers, Architecture, and Synthesis for embedded systems, CASES '02

作者： Jejurikar, Ravindra Gupta, Rajesh Center for Embedded Computer Systems Department of Information and Computer Science University of California at Irvine Irvine CA 92697 United States

ISBN: (纸本)1581135750

Slowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic Voltage Scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings. The problem of DVS in the presence of task synchronization has not yet been addressed. We compute slowdown factors for tasks which synchronize for access to shared resources. Tasks synchronize to enforce mutually exclusive access to these resources and can be blocked by lower priority tasks. We compute static slowdown factors for the tasks which guarantee meeting all the task deadlines. Our simulation experiments show on an average 25% energy gains over the known slowdown techniques. Copyright 2002 ACM.

关键词： Voltage scaling

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Don't forget memories - A case study redesigning a pattern counting ASIC circuit for FPGAs 08

Don't forget memories - A case study redesigning a pattern c...

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embedded systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

作者： Sheldon, David Vahid, Frank Department of Computer Science and Engineering UC Riverside United States Center for Embedded Computer Systems UC Irvine United States

ISBN: (纸本)9781605584706

Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to speedup performance. Many such circuits have been previously designed for acceleration via application-specific integrated circuits (ASICs). Redesigning an ASIC circuit for FPGA implementation involves several challenges. We describe a case study that highlights a common challenge related to memories. The study involves converting a pattern counting circuit architecture, based on a pipelined binary tree and originally designed for ASIC implementation, into a circuit suitable for FPGAs. The original ASIC-oriented circuit, when mapped to a Spartan 3e FPGA, could process 10 million patterns per second and handle up to 4,096 patterns. The redesigned circuit could instead process 100 million patterns per second and handle up to 32,768 patterns, representing a 10x performance improvement and a 4x utilization improvement. The redesign involved partitioning large memories into smaller ones at the expense of redundant control logic. Through this and other case studies, design patterns may emerge that aid designers in redesigning ASIC circuits for FPGAs as well as in building new high-performance and efficient circuits for FPGAs. Copyright 2008 ACM.

关键词： Application specific integrated circuits

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