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A study on the current state of the art in tool-supported UML-based static reverse engineering

A study on the current state of the art in tool-supported UM...

引用

Working Conference on Reverse Engineering

作者： R. Kollmann P. Selonen E. Stroulia T. Systa A. Zundorf Department of Computer Science University of Brethemen Germany Software Systems Laboratory Tampere University of Technology Finland Computing Science Center University of Alberta Canada Institute for Software Technical University of Braunschweig Germany

Today, software-engineering research and industry alike recognize the need for practical tools to support reverse-engineering activities. Most of the well-known CASE tools support reverse engineering in some way. The Unified Modeling Language (UML) has emerged as the de facto standard for graphically representing the design of object-oriented software systems. However, there does not yet exist a standard scheme for representing the reverse-engineered models of these systems. The various CASE tools usually adopt proprietary extensions to UML and, as a result, it is difficult, or even impossible, to ensure that model semantics remains unambiguous when working with different tools at the same time. In this paper, we examine the capabilities of the two most successful industrial-strength CASE-tools in reverse engineering the static structure of software systems and compare them to the results produced by two academic prototypes. The comparisons are carried out both manually and automatically using a research prototype for manipulating and comparing UML models.

关键词： Reverse engineering Unified modeling language Object oriented modeling computer industry computer aided software engineering Software systems Software prototyping Software standards Software design Prototypes

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Diversity techniques for concurrent error detection

Diversity techniques for concurrent error detection

引用

IEEE International Symposium on Quality Electronic Design

作者： S. Mitra E.J. McCluskey Center For Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

ISBN: (纸本)0769510256

Concurrent error detection (CED) techniques are widely used to ensure data integrity in digital systems. Data integrity guarantees that the system outputs are either correct or an error is indicated when incorrect outputs are produced. This dissertation presents the results of theoretical and simulation studies of various CED techniques. The CED schemes studied are based on diverse duplication, simple duplication of identical implementations, and error-detection techniques like parity checking. The study aimed at [1] a quantitative comparison of the effectiveness different CED schemes, and (2) developing design techniques for efficient concurrent error detection.

关键词： Failure analysis computer errors Concurrent computing Redundancy Laboratories Digital systems Error correction Analytical models Algorithm design and analysis Electromagnetic interference

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At-speed logic BIST using a frozen clock testing strategy

At-speed logic BIST using a frozen clock testing strategy

引用

IEEE International Test Conference

作者： Jongshin Shin Xiaoming Yu E.M. Rudnick M. Abramovici Center for Reliable and High-Performance Computing University of Illinois Urbana IL USA Circuits and Systems Research Laboratory Agere Systems Murray Hill NJ USA

We present a new approach to built-in self-test (BIST) for logic circuits that achieves comparable fault coverages to scan BIST with less hardware overhead and no impact on performance. We combine clock partitioning to create independent clocks with a selective freezing of clock signals to form various pipeline configurations during testing. Since no scan operations are performed, tests can be applied at the operational speed of the circuit. Experimental results are presented for several benchmark circuits to demonstrate the effectiveness of the approach.

关键词： Logic testing Built-in self-test Clocks Circuit testing Logic circuits Circuit faults Hardware Pipelines Performance evaluation Benchmark testing

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RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing

RHiNET-3/SW: an 80-Gbit/s high-speed network switch for dist...

引用

Hot Interconnects

作者： S. Nishimura T. Kudoh H. Nishi J. Yamamoto R. Ueno K. Harasawa S. Fukuda Y. Shikichi S. Akutsu K. Tasho H. Amano Co Central Research Laboratory RWCP Optical Interconnection Hitachi Laboratory Hitachi and Limited Japan Real World Computing Partnership Tsukuba Research Center Japan Department of Information and Computer Science Keio University Japan Hitachi Communication Systems Inc. Japan Synergetech Inc. UK

We have developed a prototype network switch, RHiNET-3/SW, for a RHiNET high-performance distributed parallel computing environment. It has eight I/O ports and each port provides high-speed, bi-directional 10-Gbit/s-per-port parallel optical data transmission in a distance of over 300 m. The aggregate throughput is 80 Gbit/s per board. A switch consists of a one-chip CMOS ASIC 8/spl times/8 switch LSI (SW-LSI; a 784-pin BGA package), four deskew LSIs, and eight pairs of 1.25-Gbit/s/spl times/12-channel optical interconnection modules on a single board. The switch uses a hop-by-hop retransmission mechanism and credit-based flow control to provide reliable and long-transmission-distance data communication. The deskew LSI has a skew compensation function for 10-bit parallel data channels and an 8B10B encoder/decoder. Its optical transmitter modules use an 850-nm VCSEL and a 12-channel MMF (multi-mode fiber) ribbon. RHiNET-3/SW enables high-throughput. Long-distance and flexible-flow-control network communication by means of distributed parallel computing using commercial PCs.

关键词： High-speed networks Optical switches Communication switching Parallel processing Optical interconnections Optical transmitters Data communication Large scale integration Prototypes Bidirectional control

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A reliable LZ data compressor on reconfigurable coprocessors

A reliable LZ data compressor on reconfigurable coprocessors

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IEEE Symposium on Field-Programmable Custom computing Machines, FCCM 2000

作者： Huang, Wei-Je Saxena, Nirmal McCluskey, Edward J. CENTER for Reliable Computing Computer Systems Laboratory Department of Electrical Engineering Stanford University StanfordCA94305 United States

ISBN: (纸本)0769508715

Data compression techniques based on Lempel-Ziv (LZ) algorithm are widely used in a variety of applications, especially in communications and data storage. However, since the LZ algorithm involves a considerable amount of parallel comparisons, it may be difficult to achieve a very high throughput using software approaches on general-purpose processors. In addition, error propagation due to single-bit transient errors during LZ compression causes a data integrity problem. In this paper, we present an implementation of LZ data compression on reconfigurable hardware with concurrent error detection for high performance and reliability. Our approach achieves 100Mbps throughput using four Xilinx 4036XLA FPGA chips. We have also presented an inverse comparison technique for LZ compression to guarantee data integrity with less area overhead than traditional systems based on duplication. The resulting execution time overhead and compression ratio degradation due to concurrent error detection is also minimized. © 2000 IEEE.

关键词： Digital storage

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Transient errors and rollback recovery in LZ compression

Transient errors and rollback recovery in LZ compression

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Pacific Rim International Symposium on Dependable computing

作者： Wei-Je Huang E.J. McCluskey Center For Reliable Computing Computer Systems Laboratory Department of Electrical Engineering University of Stanford Stanford CA USA

This paper analyzes the data integrity of one of the most widely used lossless data compression techniques, Lempel-Ziv (LZ) compression. In this algorithm, because the data reconstruction from compressed codewords relies on previously decoded results, a transient error during compression may propagate to the decoder and cause a significant corruption in the reconstructed data. To recover the system from transient faults, we designed two rollback error recovery schemes for the LZ compression hardware, the "reload-retry" and "direct-retry" schemes. Statistical analyses show that the "reload-retry" scheme can recover the LZ compression process from transient faults in one dictionary reload cycle with a small amount of hardware redundancy. The "direct-retry" scheme can recover normal operations with a shorter latency but with a small degradation in the compression ratio.

关键词： Decoding Hardware Data analysis Data compression Statistical analysis Transient analysis Dictionaries Redundancy Delay Degradation

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A reliable LZ data compressor on reconfigurable coprocessors

A reliable LZ data compressor on reconfigurable coprocessors

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： W.-J. Huang N. Saxena E.J. McCluskey Center For Reliable Computing Computer Systems Laboratory Department of Electrical Engineering University of Stanford Stanford CA USA

ISBN: (纸本)0769508715

Data compression techniques based on the Lempel-Ziv (LZ) algorithm are widely used in a variety of applications, especially in communications and data storage. However, since the LZ algorithm involves a considerable amount of parallel comparisons, it may be difficult to achieve a very high throughput using software approaches on general-purpose processors. In addition, error propagation due to single-bit transient errors during LZ compression causes a data integrity problem. We present an implementation of LZ data compression on reconfigurable hardware with concurrent error detection for high performance and reliability. Our approach achieves 100 Mbps throughput using four Xilinx 4036XLA FPGA chips. We also present an inverse comparison technique for LZ compression to guarantee data integrity with less area overhead than traditional systems based on duplication. The resulting execution time overhead and compression ratio degradation due to concurrent error detection is also minimized.

关键词： Coprocessors Data compression Dictionaries Throughput computer architecture Hardware Field programmable gate arrays Application specific integrated circuits Application software Degradation

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An ACS robotic control algorithm with fault tolerant capabilities

An ACS robotic control algorithm with fault tolerant capabil...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： S.-Y. Yu N. Saxena E.J. McCluskey Departments of Electrical Engineering and Computer Science Computer Systems Laboratory Stanford University Center for Reliable Computing Stanford CA USA

ISBN: (纸本)0769508715

This paper demonstrates that an adaptive computing system (ACS) is good platform for implementing robotic control algorithms. We show that an ACS can be used to provide both good performance and high dependability. An example of an FPGA-implemented dependable control algorithm is presented. The flexibility of ACS is exploited by choosing the best precision for our application. This reduces the amount of required hardware and improves performance. Results obtained from a WILDFORCE emulation platform showed that even using 0.35 /spl mu/m technology, an FPGA-implemented control algorithm has comparable performance with the software-implemented control algorithm in a 0.25 /spl mu/m microprocessor. Different voting schemes are used in conjunction with multi-threading and combinational redundancy to add fault tolerance to the robotic controller. Error-injection experiments demonstrate that robotic control algorithms with fault tolerance techniques are orders of magnitude less vulnerable to faults compared to algorithms without any fault tolerant features.

关键词： Robot control Fault tolerance Adaptive systems Programmable control Adaptive control Control systems Application software Hardware Emulation Microprocessors

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Möbius: An extensible tool for performance and dependability modeling 11th

Möbius: An extensible tool for performance and dependabilit...

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11th International Conference on Modelling Tools and Techniques for computer and Communication System Performance Evaluation, TOOLS 2000

作者： Daly, David Deavours, Daniel D. Doyle, Jay M. Webster, Patrick G. Sanders, William H. Center for Reliable and High-Performance Computing Coordinated Science Laboratory and Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign 1308 W. Main St UrbanaIL United States

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Loki: a state-driven fault injector for distributed systems

Loki: a state-driven fault injector for distributed systems

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International Conference on Dependable systems and Networks (DSN)

作者： R. Chandra R.M. Lefever M. Cukier W.H. Sanders Center for Reliable and High-Performance Computing Coordinated Science Laboratory and Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign Urbana IL USA

Distributed applications can fail in subtle ways that depend on the state of multiple parts of a system. This complicates the validation of such systems via fault injection, since it suggests that faults should be injected based on the global state of the system. In Loki, fault injection is performed based on a partial view of the global state of a distributed system, i.e. faults injected in one node of the system can depend on the state of other nodes. Once faults are injected, a post-runtime analysis, using off-line clock synchronization, is used to place events and injections on a single global timeline and to determine whether the intended faults were properly injected. Finally, experiments containing successful fault injections are used to estimate the specified measures. In addition to briefly reviewing the concepts behind Loki and its organization, we detail Loki's user interface. In particular, we describe the graphical user interfaces for specifying state machines and faults, for executing a campaign and for verifying whether the faults were properly injected.

关键词： Synchronization Clocks Distributed computing Application software User interfaces Graphical user interfaces Cost accounting Contracts Particle measurements Runtime

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