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VLSI Test Symposium

作者： S.C. Ma E.J. McCluskey Center for Reliable Computing Computer System Laboratory Departments of Electrical Engineering and Computer Engineering University of Stanford Stanford CA USA

Opens in different BiCMOS structures are analyzed here. It is shown that some opens cannot be detected by stuck-fault tests, since some transistors in BiCMOS gates do not affect the logical function of the gate. It is also shown that, in BiCMOS circuits, an open defect in a particular transistor can cause an acceleration in the wearout of another non-defective transistor.< >

关键词： BiCMOS integrated circuits Circuit faults Circuit testing MOSFETs Bipolar transistor circuits Bipolar transistors Delay Semiconductor device modeling Laboratories Failure analysis

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An environment for importance sampling based on stochastic activity networks

An environment for importance sampling based on stochastic a...

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reliable Distributed systems

作者： W.D. Obal W.H. Sanders Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

Model-based evaluation of reliable distributed and parallel systems is difficult due to the complexity of these systems and the nature of the dependability measures of interest. The complexity creates problems for analytical model solution techniques, and the fact that reliability and availability measures are based on rare events makes traditional simulation methods inefficient. Importance sampling is a well-known technique for improving the efficiency of rare event simulations. However, finding an importance sampling strategy that works well in general is a difficult problem. The best strategy for importance sampling depends on the characteristics of the system and the dependability measure of interest. This fact motivated the development of an environment for importance sampling that would support the wide variety of model characteristics and interesting measures. The environment is based on stochastic activity networks, and importance sampling strategies are specified using the new concept of the importance sampling governor. The governor supports dynamic importance sampling strategies by allowing the stochastic elements of the model to be redefined based on the evolution of the simulation. The utility of the new environment is demonstrated by evaluating the unreliability of a highly dependable fault-tolerant unit used in the well-known MARS architecture. The model is non-Markovian, with Weibull distributed failure times and uniformly distributed repair times.< >

关键词： Monte Carlo methods Stochastic processes Analytical models Discrete event simulation Availability Sampling methods Stochastic systems computer network reliability computer networks Concurrent computing

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Quality and single-stuck faults

Quality and single-stuck faults

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IEEE International Test Conference

作者： E.J. McCluskey CENTER FOR RELIABLE COMPUTING Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

The goal of IC production test is to avoid selling bad parts. The goal of fault grading is to assure that the test is so thorough that only an acceptably small fraction of shipped parts are bad. Fault grading is almos... 详细信息

关键词： Circuit faults Circuit testing Fault detection Test pattern generators Laboratories Production Integrated circuit testing Integrated circuit interconnections Inverters Delay

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Protein Secondary Structure Prediction Using Two-level Case-based Reasoning

Protein Secondary Structure Prediction Using Two-level Case-...

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1st International Conference on Intelligent systems for Molecular Biology, ISMB 1993

作者： Leng, Bing Buchanan, Bruce G. Nicholas, Hugh B. Intelligent Systems Laboratory Department of Computer Science University of Pittsburgh PittsburghPA15260 United States Pittsburgh Supper Computing Center University of Pittsburgh PittsburghPA15260 United States

ISBN: (纸本)0929280474

We have developed a two-level case-based reasoning architecture for predicting protein secondary structure. The central idea is to break the problem into two levels: first, reasoning at the object (protein) level, and using the global information from this level to focus on a more restricted problem space;second, decomposing objects into pieces (segments), and reasoning at the internal structures level;finally, synthesizing the pieces back to the objects. The architecture has been implemented and tested on a commonly used data set with 69.3% predictive accuracy. It was then tested on a new data set with 67.3% accuracy. Additional experiments were conducted to determine the effects of using different similarity matrices. Copyright © 1993, AAAI (***). All rights reserved.

关键词： Case based reasoning

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A portable parallel algorithm for VLSI circuit extraction

A portable parallel algorithm for VLSI circuit extraction

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International Symposium on Parallel Processing

作者： B. Ramkumar P. Banerjee Department of Electrical & Computer Engineering University of Iowa USA Center for Reliable and High-Perf Computing Coordinated Science Laboratory University of Illinois USA

The authors describe a new portable algorithm for parallel circuit extraction. The algorithm is built as part of the ongoing ProperCAD project: a portable object-oriented parallel environment for CAD applications that is built on top of the CHARM system. The algorithm, unlike prior approaches like PACE is asynchronous and is based on a coarse-grained dataflow execution model. Performance of circuit extraction is presented on four parallel machines: an Encore Multimax, a Sequent Symmetry, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. The extractor runs unchanged on all these machines.< >

关键词： Parallel algorithms Very large scale integration Object oriented modeling Concurrent computing Workstations Circuit testing Runtime library Portable computers Application software Parallel machines

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Applying formal methods to an embedded real-time avionics system

Applying formal methods to an embedded real-time avionics sy...

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IEEE Workshop on Real-Time Applications

作者： P.C. Clements C.L. Heitmeyer B.G. Labaw A.K. Mok Center for High Assurance Computing Systems U.S. Naval Research Laboratory Washington D.C. DC USA Department of Computer Sciences University of Technology Austin TX USA

The authors present an application of formal development methodology to an actual real-time embedded system. The formal methods used are based on Modechart a graphical state specification language for real-time systems, whose formal semantic definition provides the basis for analysis. The specifications may be automatically simulated, or verified with respect to user-provided safety, liveness, and timing assertions. The application is of non-toy size and functionality, and features many state-of-the-practice design properties, such as parallel priority-based synchronizing processes with preemption.< >

关键词： Real time systems Aerospace electronics Embedded system Formal specifications Timing Embedded computing Laboratories Safety Performance analysis Logic

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SIMPLE BOUNDS ON SERIAL SIGNATURE ANALYSIS ALIASING FOR RANDOM TESTING

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IEEE TRANSACTIONS ON computerS 1992年第5期41卷 638-645页

作者： SAXENA, NR FRANCO, P MCCLUSKEY, EJ Center for Reliable Computing ERL 460 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

It is shown that the aliasing probability is bounded above by (1 + epsilon)/L almost-equal-to 1/L (epsilon small for large L) for test lengths L less than the period, L(c), of the signature polynomial;for test lengths L that are multiples of L(c), the aliasing probability is bounded above by 1;and, for test lengths L greater than L(c) and not a multiple of L(c), the aliasing probability is bounded above by 2/(L(c) + 1). These simple bounds avoid any exponential complexity associated with the exact computation of the aliasing probability. Simple bounds also apply to signature analysis based on any linear finite state machine (including linear cellular automaton). From these simple bounds it follows that the aliasing probability in a signature analysis design using beta-intermediate signatures is bounded by ((1 + epsilon)(beta)beta(beta))/L(beta), for beta < L and L/beta < L(c). By using intermediate signatures the aliasing probability can be substantially reduced.

关键词： DUAL CODES LINEAR CODES SIGNATURE ANALYSIS WEIGHT DISTRIBUTION

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Orthogonal built-in self-test

Orthogonal built-in self-test

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IEEE Compcon

作者： L. Avra Center for Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

The author introduces a new way to organize memory elements into scan chains for built-in self-testable data path logic. The goal of the procedure is to minimize the hardware overhead and performance impact associated with pseudo-random built-in self-test (PR-BIST) techniques by organizing the memory elements such that some of the logic required for BIST and scan operations is also used during normal operation. The author identifies function types that are well suited for implementation with the register designs required for BIST and shows that these function types are found in data path designs. Functional use is made of the BIST logic by organizing the memory elements in the design into orthogonal scan chains. A data path design example is used to compare an implementation using a normal BIST configuration to one using the orthogonal configuration.< >

关键词： Built-in self-test Hardware Costs Logic testing Organizing Logic design Automatic testing Shift registers Laboratories Life testing

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ProperSYN: A portable parallel algorithm for logic synthesis

ProperSYN: A portable parallel algorithm for logic synthesis

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IEEE International Conference on computer-Aided Design

作者： De Ramkumar Banerjee Center for Reliable & High-Perf. Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Electrical & Computer Engineering University of Iowa Iowa IA USA

An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asynchronous message driven computing model with no synchronizing barriers, and hence it is scalable to a larger number of processors. Also, the algorithm is portable across a wide variety parallel machines. Experimental results on various parallel machines are presented. The algorithm is built around a well-defined sequential algorithm interface such that there can be benefits from future expansion of the sequential algorithm.< >

关键词： Design automation Parallel algorithms

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Temperature dependence and material properties of InGaAsP/lnP mirrors 4

Temperature dependence and material properties of InGaAsP/ln...

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LEOS 1992 Summer Topical Meeting Digest on Broadband Analog and Digital Optoelectronics, Optical Multiple Access Networks, Integrated Optoelectronics, and Smart Pixels - 4th International Conference on Indium Phosphide and Related Materials, IPRM 1992

作者： Dudley, J.J. Crawford, D.L. Bowers, J.E. Silvestre, P. Robinson, G.Y. Department of Electrical and Computer Engineering University of California Santa BarbaraCA93106 United States Jet Propulsion Laboratory PasadenaCA91109 United States Department of Electrical Engineering Center for Optoelectronic Computing Systems Fort CollinsCO80523 United States

ISBN: (纸本)0780305221

We analyze the temperature dependence and material properties of InGaAsP/lnP quarter wave mirrors used in optoelectronic devices such as surface emitting lasers and resonant cavity photodetectors. We measure the variation in center wavelength of the mirrors as the temperature changes over an 80 °C range. The peak reflectivity and bandwidth of the mirrors are measured as a function of the number of layers. © 1992 IEEE.

关键词： III-V semiconductors

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