The goal of IC production test is to avoid selling bad parts. The goal of fault grading is to assure that the test is so thorough that only an acceptably small fraction of shipped parts are bad. Fault grading is almos...
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The goal of IC production test is to avoid selling bad parts. The goal of fault grading is to assure that the test is so thorough that only an acceptably small fraction of shipped parts are bad. Fault grading is almost always based on a single-stuck fault, ssf, model.< >
We have developed a two-level case-based reasoning architecture for predicting protein secondary structure. The central idea is to break the problem into two levels: first, reasoning at the object (protein) level, and...
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The authors describe a new portable algorithm for parallel circuit extraction. The algorithm is built as part of the ongoing ProperCAD project: a portable object-oriented parallel environment for CAD applications that...
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The authors describe a new portable algorithm for parallel circuit extraction. The algorithm is built as part of the ongoing ProperCAD project: a portable object-oriented parallel environment for CAD applications that is built on top of the CHARM system. The algorithm, unlike prior approaches like PACE is asynchronous and is based on a coarse-grained dataflow execution model. Performance of circuit extraction is presented on four parallel machines: an Encore Multimax, a Sequent Symmetry, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. The extractor runs unchanged on all these machines.< >
The authors present an application of formal development methodology to an actual real-time embedded system. The formal methods used are based on Modechart a graphical state specification language for real-time system...
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The authors present an application of formal development methodology to an actual real-time embedded system. The formal methods used are based on Modechart a graphical state specification language for real-time systems, whose formal semantic definition provides the basis for analysis. The specifications may be automatically simulated, or verified with respect to user-provided safety, liveness, and timing assertions. The application is of non-toy size and functionality, and features many state-of-the-practice design properties, such as parallel priority-based synchronizing processes with preemption.< >
作者：
L. AvraCenter for Reliable Computing
Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA
The author introduces a new way to organize memory elements into scan chains for built-in self-testable data path logic. The goal of the procedure is to minimize the hardware overhead and performance impact associated...
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The author introduces a new way to organize memory elements into scan chains for built-in self-testable data path logic. The goal of the procedure is to minimize the hardware overhead and performance impact associated with pseudo-random built-in self-test (PR-BIST) techniques by organizing the memory elements such that some of the logic required for BIST and scan operations is also used during normal operation. The author identifies function types that are well suited for implementation with the register designs required for BIST and shows that these function types are found in data path designs. Functional use is made of the BIST logic by organizing the memory elements in the design into orthogonal scan chains. A data path design example is used to compare an implementation using a normal BIST configuration to one using the orthogonal configuration.< >
An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asy...
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An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asynchronous message driven computing model with no synchronizing barriers, and hence it is scalable to a larger number of processors. Also, the algorithm is portable across a wide variety parallel machines. Experimental results on various parallel machines are presented. The algorithm is built around a well-defined sequential algorithm interface such that there can be benefits from future expansion of the sequential algorithm.< >
We analyze the temperature dependence and material properties of InGaAsP/lnP quarter wave mirrors used in optoelectronic devices such as surface emitting lasers and resonant cavity photodetectors. We measure the varia...
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The authors have measured and modeled the temperature characteristics and material properties of quarter wavelength mirrors made using InP and InGaAsP. The center wavelength of the mirror moves at 0.110 nm/ degrees C,...
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The authors have measured and modeled the temperature characteristics and material properties of quarter wavelength mirrors made using InP and InGaAsP. The center wavelength of the mirror moves at 0.110 nm/ degrees C, in good agreement with the theory. This is an important result for the thermal design of such devices as VCSELs. This result can be used to find the shift in the resonant mode of the cavity or the change in penetration depth of the mirror with temperature. The authors have also characterized the reflectivity and bandwidth of this mirror as a function of the number of layers. Using selective wet chemical etchants, they removed one layer at a time and then measured the spectrum of the mirror. From this structural analysis, it was found that the center wavelength is much more sensitive than the bandwidth or peak reflectivity in detecting drift in layer thicknesses. This technique can be used to find the actual reflectivity for different numbers of layers without resorting to several expensive, time-consuming mirror growths. The measured reflectivity and bandwidth are in good agreement with theory.< >
Recently derived upper bounds on the aliasing probability for serial signature analysis using the Bernoulli error model are reviewed. Since the bit error probability p is unrestricted in general, upper bounds independ...
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Recently derived upper bounds on the aliasing probability for serial signature analysis using the Bernoulli error model are reviewed. Since the bit error probability p is unrestricted in general, upper bounds independent of p are emphasized. It is also shown that even for exhaustive testing, the aliasing probability for non-primitive polynomials with short periods does not reach its asymptotic value of all p.< >
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