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IEEE International Test Conference

作者： L. Avra Center for Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering Computer Science University of Stanford Stanford CA USA

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Bridging, transition, and stuck-open faults in self-testing CMOS checkers

Bridging, transition, and stuck-open faults in self-testing ...

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International Symposium on Fault-Tolerant computing (FTCS)

作者： S.D. Millman E.J. McCluskey Center For Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

The consequences of bridging, transition, and stuck-open faults in self-testing checkers designed only for single stuck-at faults are examined. A methodology for design that guarantees that the checkers will be self-testing in the presence of bridging, transition and stuck-open faults is established. This methodology is applied to several implementations of self-testing checkers. Simulations confirm that these checkers are self-testing in the presence of bridging, transition, and stuck-open faults. The problems associated with testing the checkers in the presence of non-stuck-at faults and the problems that result from reducing the number of checker outputs from two to one are discussed. It is shown that self-testing checkers designed for stuck-at faults will remain self-testing in the presence of nonclassical faults.< >

关键词： Built-in self-test Circuit faults Electrical fault detection Fault detection Automatic testing Runtime computer errors CMOS technology Laboratories Design methodology

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REFINED BOUNDS ON SIGNATURE ANALYSIS ALIASING FOR RANDOM TESTING

REFINED BOUNDS ON SIGNATURE ANALYSIS ALIASING FOR RANDOM TES...

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IEEE International Test Conference

作者： N.R. Saxena P. Franco E.J. McCluskey Center for Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

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Bounds on signature analysis aliasing for random testing

Bounds on signature analysis aliasing for random testing

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International Symposium on Fault-Tolerant computing (FTCS)

作者： N.R. Saxena P. Franco E.J. McCluskey Center for Reliable Computing ERL 460 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

Simple bounds on the aliasing probability for serial signature analysis are presented. To motivate the study, it is shown that calculation of exact aliasing is NP-hard and that coding theory does not necessarily help. It is shown that the aliasing probability is bounded above by 2/(L+2) for test lengths L less than the period, L/sub c/, of the signature polynomials; for test lengths L that are multiples of L/sub c/, the aliasing probability is bounded above by 1; and, for test lengths L greater than L/sub c/ and not a multiple of L/sub c/, the aliasing probability is bounded above by 2/(L/sub c/+1). These simple bounds avoid any exponential complexity associated with the exact computation of the aliasing probability. Simple bounds also apply to signature analysis based on any linear finite state machine (including linear cellular automata).< >

关键词： Circuit faults Circuit testing Compaction Polynomials Feedback Very large scale integration Automata Laboratories computer errors Automatic testing

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Intelligent mapping of communicating processes in distributed computing systems 91

Intelligent mapping of communicating processes in distribute...

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Proceedings of Supercomputing '91

作者： Ieumwananonthachai, Arthur Aizawa, Akiko N. Schwartz, Steven R. Wah, Benjamin W. Yan, Jerry C. Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaing 1101 West Springfield Avenue Urbana IL Sterling Federal Systems Inc. and NASA Ames Research Center Moffett Field CA

ISBN: (纸本)0818621583

The authors present TEACHER 4.1, a system for automatically designing heuristics that map a set of communicating processes on a real-time distributed computing system. The problem of optimal process mapping is NP-hard and involves the optimal routing of messages from one computer to another. The design of efficient and robust heuristics is often ad hoc and is guided by intuition and experience of the designers. The authors develop a statistical method to systematically explore the space of possible heuristics for process mapping. The method operates under a specified time constraint and intends to get the best possible heuristics while trading between the solution quality and the execution time of the process mapping heuristics. The prototype for process mapping is extended from post-game analysis, a system that uses a set of user-specified rules for generating new mappings. It tunes parameters of these rules and proposes new heuristics for process mapping. Simulations show that there is significant improvement in performance through systematic and automatic exploration of the space of heuristics.

关键词： computer systems, Digital

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Parallel switch-level simulation for VLSI

Parallel switch-level simulation for VLSI

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European Conference on Design Automation

作者： R.B. Mueller-Thuns D.G. Saab J.A. Abraham Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Computer Engineering Research Center University of Texas Austin Austin TX USA

Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Their target machines are medium-grain multiprocessors (shared memory or message passing machines) and they only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. Efficient strategies are introduced for circuit partitioning as well as the corresponding simulation algorithms. In the authors' approach, they try to minimize the total number of synchronizations between processors, as well as ensure portability and scalability. A preprocessor and simulator were implemented and good performance was obtained for a set of benchmarks. The problem of tight coupling between processors that evaluate a strongly connected component in the circuit in a distributed fashion is highlighted.< >

关键词： Very large scale integration Computational modeling Circuit simulation Concurrent computing Switching circuits Process design Acceleration computer simulation Message passing Partitioning algorithms

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Harvest rate of reconfigurable pipelines

Harvest rate of reconfigurable pipelines

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IEEE International Symposium on Defect and Fault Tolerance in VLSI systems

作者： Weiping Shi Ming-Feng Chang W. Kent Fuchs Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science and Information Engineering National Chiao Tung University Taiwan

Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are provided for reconfiguration, the authors calculate the expected percentage of pipelines they can harvest after reconfiguration. By modeling the 'shifting' reconfiguration as weighted chains in a lattice and applying poset theory, they give upper and lower bounds for the harvest rate as a function of m and n.< >

关键词： Pipelines Wires Lattices Very large scale integration Switches Algorithm design and analysis Parallel architectures Supercomputers Equations Engineering management

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Yield enhancement of wafer scale integrated arrays

Yield enhancement of wafer scale integrated arrays

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International Conference on Wafer Scale Integration

作者： J. Narasimhan K. Nakajima C.S. Rim A.T. Dahbura E.E. Department & Systems Research Center University of Maryland College Park MD USA Design Automation Systems Section Semiconductor Technology Division Electronics and Telecommunications Research Institute Daejeon South Korea E.E. Department Systems Research Center & Institute for Advanced Computer Studies University of Maryland College Park MD USA Computing Systems Research Laboratory AT and T Bell Laboratories Inc. Murray Hill NJ USA

In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step this placement is reconfigured so that the circuit is mapped onto the defect-free portion of a defective PGA chip with the same architecture. In the present work, the authors consider the problem of yield enhancement along the same lines as above not only for PGAs but also for wafer-scale-integrated arrays. A heuristic algorithm for reconfiguration based on a graph-theoretic formulation of the problem and a polynomial-time exact algorithm for a special case of the problem are presented. The reconfiguration algorithms are evaluated by comparing the routability and wire length of the reconfigured and initial placements of the circuit.< >

关键词： Electronics packaging Integrated circuit yield Design automation Computational modeling Circuit simulation computer simulation Simulated annealing Heuristic algorithms Polynomials

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HIGH-SPEED GAAS/ALGAAS OPTOELECTRONIC DEVICES FOR computer-APPLICATIONS

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IBM JOURNAL OF RESEARCH AND DEVELOPMENT 1990年第4期34卷 568-584页

作者： HARDER, CS VANZEGHBROECK, BJ KESLER, MP MEIER, HP VETTIGER, P WEBB, DJ WOLF, P IBM Research Division Zurich Research Laboratory Ruschlikon Switzerland Department of Electrical and Computer Engineering and the Optoelectronic Computing Systems Center University of Colorado Colorado

We present an overview, mainly of work in our laboratory, of low-threshold GaAs/AlGaAs quantum-well laser diodes and GaAs metal-semiconductor-metal photodetectors—two optoelectronic devices which show good promise for use in computer-related communication. Present-day telecommunication device technology (based on InP materials) is not well suited to the requirements of optical data communication among and within computers because the computer environment is much more demanding. It imposes a higher ambient temperature on the devices, and requires denser packaging and smaller power dissipation per device, as well as a high degree of parallelism. The GaAs/AlGaAs device technology is ideally suited to this task because of the possibility of integration of arrays of high-speed, low-threshold laser diodes and high-speed photodetectors with high-performance electronic circuits.

关键词： Optoelectronic Devices

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Behavioral synthesis of testable systems with VHDL

Behavioral synthesis of testable systems with VHDL

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IEEE Compcon

作者： L. Avra E.J. McCluskey Center For Reliable Computing Computer Systems Laboratory Departments of Elecmcal Engineering and Computer Science University of Stanford Stanford CA USA

A methodology for automatically synthesizing a testable RTL (register-transfer-level) hardware specification from a behavioral VHDL (VHSIC hardware description language) specification is presented. Behavioral synthesis is described. It consists of the automatic creation of a hardware specification, given an input specification that describes how the hardware operates in response to its current state and the states of its input signals. The synthesis methodology includes techniques for ensuring that the resulting hardware is testable. The techniques used for mapping the input behavioral model to hardware assume that the resulting hardware is fully synchronous and serial scan compatible. The synthesis process recognizes expressions and operations in the behavioral model and maps them to corresponding hardware components that are included in a separate VHDL library.< >

关键词： System testing Hardware design languages Built-in self-test Very high speed integrated circuits Signal synthesis Equations Multiplexing Libraries Laboratories Reliability engineering

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