In switch-level simulation, nodes carry a charge on their parasitic capacitance from one evaluation to the next, which gives them a memory quality. A node is classified as temporary if its memory aspect is lost and ca...
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In switch-level simulation, nodes carry a charge on their parasitic capacitance from one evaluation to the next, which gives them a memory quality. A node is classified as temporary if its memory aspect is lost and cannot affect the circuit operation, whereas a node is classified as a memory node if the memory of the node is maintained and can affect the circuit operation. Accurate classification of nodes into temporary and memory nodes increases the performance of compiled simulators and high-level model generators. An approach for reliable automatic classification of nodes in a switch-level description is introduced. Both an exhaustive, exponential-time algorithm and a polynomial-time heuristic are presented. The heuristic was implemented and tested for several large circuits, including a commercial microprocessor. For this processor, the proposed heuristics identified an average of 92% of all nodes as temporary nodes. The heuristic was applied in a high-level model generator and significantly increased its performance.< >
An analysis is presented of error detection characteristics when galois checksums and arithmetic checksums are used simultaneously. By generalizing previous results, it is shown that galois checksums and arithmetic ch...
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An analysis is presented of error detection characteristics when galois checksums and arithmetic checksums are used simultaneously. By generalizing previous results, it is shown that galois checksums and arithmetic checksums exhibit orthogonal characteristics with respect to error detection. An analytic proof of orthogonality is presented for certain restricted cases. These orthogonal characteristics hold good for equally likely errors, restricted column errors, and restricted word errors. Double-length galois checksums are compared with combined arithmetic and galois checksums.< >
The critical path technique for determining the single stuck-at faults detected by a test is extended to multiple faults by defining masking paths. A masking tree is used to represent the masking relationships among i...
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The critical path technique for determining the single stuck-at faults detected by a test is extended to multiple faults by defining masking paths. A masking tree is used to represent the masking relationships among individual faults. These relationships are then used to determine which multiple faults are actually detected by a test.< >
The authors present a low-cost self-test and self-diagnosis architecture for locating both defective chips and bad interconnects on a printed-circuit board. It is assumed that the boundary scan method developed by the...
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The authors present a low-cost self-test and self-diagnosis architecture for locating both defective chips and bad interconnects on a printed-circuit board. It is assumed that the boundary scan method developed by the Joint Task Action Group (JTAG) is applied to all chips on the board. To achieve high fault coverage, the proposed method uses pseudorandom patterns from a cellular automaton to locate defective chips, and walking sequences to locate bad interconnects. It is shown that the effectiveness of this method depends on the type of circuits to be tested.< >
Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to ge...
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Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required.< >
Recent developments in the logic design courses in the computersystemslaboratory at Stanford University are described. The courses include an introductory undergraduate lecture and laboratory course, an advanced und...
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Recent developments in the logic design courses in the computersystemslaboratory at Stanford University are described. The courses include an introductory undergraduate lecture and laboratory course, an advanced undergraduate laboratory, and a graduate lecture and CAE (computer-aided engineering) laboratory course.< >
A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault...
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A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher?all irredundant multiple as well as single stuck faults are detected. The test patterns are easily generated algorithmically either by program or hardware.
The number of devices that can be fabricated on a single VLSI chip has been increasing each year without a proportional increase in the number of I/O pins. This density growth aggravates the already difficult problem ...
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The number of devices that can be fabricated on a single VLSI chip has been increasing each year without a proportional increase in the number of I/O pins. This density growth aggravates the already difficult problem of testing such microcircuits. This situation has resulted in a widespread belief that economical testing can only be obtained if a testing strategy is adopted during the initial chip design. A survey of the major design techniques available for enhancing chip "testability" is presented here. Such techniques are usually referred to as "design for testability" methods.
A system of checkers is designed for concurrent error detection in large PLA's. This system combines concurrent error detection with off-line functional testing of the PLA by using the same checker hardware for bo...
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A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present-day automatic test pattern generation (ATPG) programs. Fault...
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