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Wigner-Ville distribution and cross Wigner-Ville distribution of noisy signals

Journal of Systems Engineering and Electronics 2008年第5期000卷

作者： Chen Guanghua Ma Shiwei Liu Ming Zhu Jingming Zeng Weimin Key Laboratory of Advanced Display and System Applications Ministry of Education & Microelectronic Research and Development CenterShanghai Univ.Shanghai 200072P.R.China

The Wigner-Ville distribution (WVD) and the cross Wigner-Ville distribution (XWVD) have been shown to be efficient in the estimation of instantaneous frequency (IF).But the statistical result of the IF estimation from XWVD peak is much better than using WVD *** reason is given from a statistical point of *** studies show that XWVD of the analyzed signal can be estimated from XWVD of the noise-contaminated *** estimation is unbiased,and the variance is equal to that of *** this case,WVD cannot be estimated from WVD of the noise-contaminated ***,higher SNR is required when WVD is used to analyze signals.

关键词： Wigner-Ville distribution cross Wigner-Ville distribution instantaneous frequency expectation vari-ance

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The Application of Two-dimensional Cellular Automata in Logic BIST

The Application of Two-dimensional Cellular Automata in Logi...

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International Symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Jinyi Zhang Jianghua Gui Yun Feng Key Laboratory of Advanced Display and System Applications Ministry of Education Microelectronic Research & Development Center Shanghai University Shanghai China Key Laboratory of Advanced Display and System Applications Ministry of Education Microelectronic Research & Development Center Shanghai University Shanghai China

With the increase in complexity of VLSI and the test cost of automatic test equipment (ATE), logic built-in self-test (BIST) has been widely applied. In order to reduce the test time of logic BIST, logic BIST with multiple scan chains has been proposed. However, the main shortcoming of logic BIST with multiple scan chains is low fault coverage (FC). A novel two-dimensional cellular automata (2-DCA), which is called two-dimensional restricted vertical neighbor cellular automata (2-DRVNCA), is proposed to resolve this problem. Using this 2-DRVNCA as pseudorandom test pattern generator (PRPG), high FC can be achieved. In the last, this PRPG is applied on some benchmark circuits of ISCAS'89, and average FC (82% ~ 89%) is obtained.

关键词： Built-in self-test Logic testing Very large scale integration Automatic testing Costs Automatic test equipment Automatic logic units Circuit faults Test pattern generators Benchmark testing

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Integrating ADC IP in a SoC and Its Verification

Integrating ADC IP in a SoC and Its Verification

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International Symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Yueli Hu Wenyi Jing Ying Liu Microelectronic Research & Development Center Key Laboratory of Advanced Display and System Applications Shanghai University Shanghai China

More and more analog and mixed-signal (AMS) blocks are integrated into SoC (system-on-chip) platform due to intense market competition. In this paper we proposed a method for IP integration of mixed-signal SoCs. With continuous growing of design scale and complex validation of mixed-signal functions, a new verification methodology for large mixed-signal SoC designs using Synopsys Discovery AMS platform is given to handle the daunting challenge. We will give a brief introduction with an example of SoC design which contains a reusable 10-bit SAR ADC IP block. And the detailed flow of using NanoSim-VCS co-simulation environment for the example is elaborated.

关键词： Pulse width modulation Testing System-on-a-chip Time to market Microcontrollers Microelectronics Laboratories Displays Integrated circuit manufacture Semiconductor device manufacture

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A Test Platform for Turbo Encoder & Decoder Based on S3C2410

A Test Platform for Turbo Encoder & Decoder Based on S3C2410

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International Symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Ming Li Jing-sai Jiang Ming-ming Peng Fa-yu Wan Microelectronic Research & Development Center Key Laboratory of Advanced Display and System Applications Ministry of Education Shanghai University China

Encoder & decoder are absolutely necessary and important in digital communications. This article introduces one kind of test system, which can estimate the performance of turbo encoder & decoder. It includes system composition principle, hardware and software architecture and test function. The practicability of the system is strong and its connection is convenient. After adjusting the test software, the system can also test other types of encoder & decoder.

关键词： Embedded system Operating systems Iterative decoding System testing Hardware Embedded software Microprocessors Energy consumption Application software Software testing

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Totally Self Checking FSM Based on Convolutional Codes

Totally Self Checking FSM Based on Convolutional Codes

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International Symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Ming Li Fa-Yu Wan Jin-Sai Jiang Ming-Ming Peng Microelectronic Research & Development Center Key Laboratory of Advanced Display and System Applications Ministry of Education Shanghai University China

In this paper a new technique for designing totally self- checking finite state machines is presented using convolutional codes. In order to correct the fault, we propose a novel scheme which can not only detect, but also correct errors occurred in FSM transition. More specifically, we demonstrate the FSMs hardware which can be reused based on convolutional code partitioning and we formulate the optimization problem of maximizing hardware reusability. Synthesis results produced by our proposed procedure for the MCNC'89 FSM benchmark circuits show an average 20% reduction in literal counts compared to previous techniques. Moreover, we realize the IP core of the self-checking module by SMIC 0.25μm technology and also simulate its function in FPGA.

关键词： Convolutional codes Hardware Automata Circuit faults Electrical fault detection Fault detection Error correction Circuit synthesis Circuit simulation Field programmable gate arrays

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A Pipeline Sliding Window Max-Log-Map Turbo Decoder

A Pipeline Sliding Window Max-Log-Map Turbo Decoder

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International Symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Ming Li Ming-ming Peng Jing-sai Jiang Fa-yu Wan Microelectronic Research & Development Center Key Laboratory of Advanced Display and System Applications Ministry of Education Shanghai University Shanghai China

Turbo codes have become an attractive forward error correction scheme for wireless communication systems. MAP algorithm is the optimization algorithm for turbo-codes. But its implementation is complex. Max-Log-MAP algorithm is a sub-optimization algorithm of turbo-codes, which offers good compromise between performance and complexity for implementation. The authors present a re configurable turbo decoder based on Max-Log-MAP algorithm implemented with sliding window method and pipeline architecture. The sliding window (SW) method can reduce memory size. Pipeline decoding schemes can reduce decoding delay and improve throughput. The structure we proposed can reduce decoding delay obviously. It can be used in wireless communication.

关键词： Pipelines Turbo codes Iterative decoding Delay Wireless communication Throughput Microelectronics Laboratories Displays Forward error correction

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Design of SSCMP with Arbiter and Shared Data Memory Interrupt

Design of SSCMP with Arbiter and Shared Data Memory Interrup...

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International Symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Yueli Hu Ying Liu Wenyi Jing Microelectronic Research & Development Center Key Laboratory of Advanced Display and System Applications Ministry of Education Shanghai University Shanghai China

In the machine vision system, a common and effective way to solve high complexity and huge throughput of image processing arithmetic computation is to adopt instruction-level-parallel scheme through multiple MCUs with the single-threading architecture. Based on it, this paper proposed a kind of symmetric single-chip multiprocessor (SSCMP) architecture, which composed of four subprocessors and one solution for on-chip arbiter and shared data memory interrupt (SDMI). Each subprocessor could work in cooperant and also was completely independent mode. What's more, the proposed architecture set up a shared space for command transfering and data exchanging. An arbiter judgment scheme and effective interrupt access mechanism were introduced to reduce the burden of data exchange and eliminate competitions between the subprocessors.

关键词： Signal processing Hardware Machine vision Image processing Computer architecture Process control Costs Registers Microelectronics Laboratories

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Design of On-Chip Debug Module Based on MCU

Design of On-Chip Debug Module Based on MCU

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International Symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Yue-li Hu Ke-xin Zhang Key Laboratory of Advanced Display and System Applications (Shanghai University) Ministry of Education Microelectronic Research and Development Center Shanghai China

A design method of embedded OCD (On-Chip Debugging) based on Intel 8051 MCU architecture is proposed. The OCD module named E-OCD-SFRB (Enhanced OCD module with SFR (Special Function Register) Breakpoint Function) is integrated into an existing MCU core, implementing several debugging function. The method we proposed is able to switch from running mode and debugging mode conveniently by controlling the debugging enable port and also enables controlling the MCU core in debugging mode by additional SFR. The function of SFR breakpoint is added, so we could trace the particular SFR, this is the reinforcement to the exiting OCD methods. The principles of E-OCD-SFR_B and detailed implemental method and simulation solution based on EDA platform are presented and validated. The simulation result indicates the completely observing and controlling to the core is achieved without any effect to original functions of the system.

关键词： Debugging Switches Clocks Ice System-on-a-chip Embedded system Emulation Monitoring Communication system control Registers

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research on the models of OLED-On-Silicon Pixel Circuits

Research on the Models of OLED-On-Silicon Pixel Circuits

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International Symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Li-min Yan Hao Wang Key Laboratory of Advanced Display & System Applications Ministry of Education Shanghai University Microelectronic Research and Development Center Shanghai University Shanghai China

In modern information society, the display devices play an important role. Presently, Organic Light-Emitting Diode (OLED) has been emphasized and regarded as one of the best technology for its many advantages, such as active-matrix driver mode, high brightness, fast response time, high efficiency, wide visual angle, thin and light-weight etc. Much work of this paper has been done in AM-OLED technology, mainly focusing on the models of AM-OLED pixel circuit structure design and parameters assurance, AC-driving pixel circuit design and application. This research is prepared for integrated peripheral driving circuit design and application in the future.

关键词： Organic light emitting diodes Flat panel displays Thin film transistors Light emitting diodes Active matrix technology Brightness Threshold voltage Circuit synthesis Liquid crystal displays Active matrix organic light emitting diodes

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Reducing the Power Consumption of the AES S-Box by SSC

Reducing the Power Consumption of the AES S-Box by SSC

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第三届IEEE无线通讯、网络技术暨移动计算国际会议

作者： Jinyi Zhang Qinghua Zuo Tianbao Zhang Key Laboratory of Advanced Display and System Applications (Shanghai University) Ministry of Education Microelectronic Research & Development Center Shanghai University No.149 Yanchang Road Shanghai 200072 P.R.China

The advanced Encryption Standard (AES) algorithm has been accepted as the default choice in present security services. The S-Box as the key part in AES plays an important role for low-power design in the hardware implementation of the algorithm. About 75％ power consumption of an AES core is caused by the S-Box, so reducing the power of the S-Box is very efficient for the low-power design of the AES core. In this paper, the bus coding technique called Sequence-Switch Coding (SSC) is applied in the S-Box design. Input data are encoded in a certain sequence to reduce the transitions of the S-Box circuits. As a result, the power consumption in the combinational logic is brought down. The verification results show that about 10％ power has been reduced averagely in the experimental S-Box.

关键词： S-Box sequence-switch coding (SSC) AES

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