Interpolation is the main bottleneck in AVS real-time high definition video encoder for its high memory bandwidth and large calculation complexity caused by the new coding features of variable block size and 4-tap fil...
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Background. PTPH1 is a protein tyrosine phosphatase expressed in T cells but its effect on immune response is still controversial. PTPH1 dephosphorylates TCRzeta in vitro, inhibiting the downstream inflammatory signal...
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An improved modular multiplication algorithm based on the interleaved multiplication is presented in this paper. Carry save addition (CSA), redundant representation, a fast lookup table and a counter register are used...
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The Wigner-Ville distribution (WVD) and the cross Wigner-Ville distribution (XWVD) have been shown to be efficient in the estimation of instantaneous frequency (IF). But the statistical result of the IF estimati...
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The Wigner-Ville distribution (WVD) and the cross Wigner-Ville distribution (XWVD) have been shown to be efficient in the estimation of instantaneous frequency (IF). But the statistical result of the IF estimation from XWVD peak is much better than using WVD peak. The reason is given from a statistical point of view. Theoretical studies show that XWVD of the analyzed signal can be estimated from XWVD of the noise-contaminated signal. The estimation is unbiased, and the variance is equal to that of noise. In this case, WVD cannot be estimated from W-VD of the noise-contaminated signal. Therefore, higher SNR is required when WVD is used to analyze signals.
Convolutional code and Viterbi decoding is one of the methods used for channel coding. Convolutional coding is widely used in many aspects because of its excellent performance. However, both the coding algorithm and h...
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Convolutional code and Viterbi decoding is one of the methods used for channel coding. Convolutional coding is widely used in many aspects because of its excellent performance. However, both the coding algorithm and hardware implementation are very complex. Along with the continuous deepening of SOC design, hardware-software co-design technology has become more and more important as one part of SOC design. A hardware-software platform used for the design of the Viterbi decoder is proposed in this paper. The platform includes embedded software, hardware acceleration, and peripheral interface. Good practicality and powerful verification functions are proved, and optimum design for the Viterbi decoder can be achieved by using the platform.
The paper describes a four-order delta-sigma modulation (DSM) with 15 levels quantizer which is used in a 24-bit 44.1-kHz sample-rate audio digital-to-analog converter (DAC). An odd level quantizer has been chosen ins...
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The paper describes a four-order delta-sigma modulation (DSM) with 15 levels quantizer which is used in a 24-bit 44.1-kHz sample-rate audio digital-to-analog converter (DAC). An odd level quantizer has been chosen instead of an even level to reduce quantization noise. The noise transfer function (NTF) is designed to have the zeros optimally in order to increase DR. The peak SNR of the DSM is about 130 dB, which is enough for an audio DAC designed with a 0.35 um CMOS technology.
Multi-core processor is widely used on the server and desktop computer nowadays. This paper describes the structure of a cache crossbar which used in the multi-core processor SPARC T2. The cores can use the cache cros...
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Multi-core processor is widely used on the server and desktop computer nowadays. This paper describes the structure of a cache crossbar which used in the multi-core processor SPARC T2. The cores can use the cache crossbar to exchange the data in the L2 cache banks. The multi cores can communicate among each other core by sharing the data in the L2 cache banks. And with the analysis of the CCX, this paper provides a protocol for connecting multi cores and cache banks. The cache crossbar is implemented in SMIC 0.13 mum with design compiler and can run at 200 MHz.
CMOS image sensor has experienced explosive growth in recent years. As increasing of number of pixel scale and complexities of circuit, testability of image sensor chip has become an important problem that must be dea...
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CMOS image sensor has experienced explosive growth in recent years. As increasing of number of pixel scale and complexities of circuit, testability of image sensor chip has become an important problem that must be dealt with by both design and test engineers. A systematic approach to handle testability of CMOS image sensor circuits is urgently needed, because current test methods less address this domain. In this paper, a uniform and systematic approach is explored to the testability problem of CMOS image sensor, and it covers the image sensor defect analysis, fault model definition and test system design. The experimental data shows the fault coverage can be up to 99.3%.
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