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DFE: Deep Flow Embedding for Robust Network Traffic Classification

IEEE Transactions on Network Science and Engineering 2025年第3期12卷 1597-1612页

作者： Wang, Zhijiong Zhang, Anguo Li, Hung Chun Yin, Yadong Chen, Wei Lam, Chan Tong Mak, Peng Un Vai, Mang I. Gao, Yueming Pun, Sio Hang Zhuhai UM Science and Technology Research Institute Lingyange Semiconductor Incorporated Joint Laboratory Zhuhai519031 China Lingyange Semiconductor Inc. Zhuhai519030 China University of Macau State Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics 999078 China Fuzhou University School of Physics and Information Engineering Fuzhou350108 China Fudan University Center for Intelligent Medical Electronics School of Information Science and Technology Human Phenome Institute Shanghai200437 China Fudan University Human Phenome Institute Shanghai200437 China Macau Polytechnic University Faculty of Applied Sciences 999078 China University of Macau Department of Electrical and Computer Engineering Faculty of Science and Technology 999078 China Fuzhou University Key Lab of Medical Instrumentation and Pharmaceutical Technology of Fujian Province Fuzhou350108 China

People's inc.easing demand for high-quality network services has prompted the continuous attention and development of network traffic classification (NTC). In recent years, deep flow inspection (DFI) is considered to be the most effective and promising method to solve the NTC. However, DFI still cannot effectively address the problem of changes in flow characteristics of complex packet flows and the discovery of new traffic categories. In this paper, we propose a metric learning based deep learning solution with feature compressor, named deep flow embedding (DFE). The feature compressor is used to compress the feature information transmitted layer by layer in DL backbone while maintaining the computational accuracy, so that the backbone can remove as much noise, redundancy, and other irrelevant information from the input data as possible, and achieve more robust feature extraction of network traffic flow. The deep learning (DL) backbone generates an embedding vector for each network packet flow. Then the embedding vector is compared with the vector template preset for each traffic type in the template library to determine the category of the packet flow. Experimental results verify that our method is more effective than the traditional DFI methods in overcoming the problems of flow characteristics variation and new category discovery. © 2013 IEEE.

关键词： Network embeddings

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A NATURAL LANGUAGE programming SYSTEM FOR TEXT PROCESSING

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IEEE TRANSACTIONS ON ENGINEERING WRITING AND SPEECH 1968年第2期EW11卷 45-&页

作者： BARNETT, MP RUHSAM, WM Graphic Systems Applied Research Laboratory RCA Laboratories David Sarnoff Research Center Princeton NJ USA Systems Programming and Operations Research Group RCA Service Company Inc. Cherry Hill NJ USA

A " basic English" to enable editors, writers, librarians, educators, and others to instruct computers to perform mechanical text processing conveniently has been defined (see Tables II to V for partial summary). It has been given the name SNAP (Stylized Natural Procedural) language for reference. A processor that executes procedures expressed in a subset of this language has worked for some months on several computers. It was used successfully last semester by 40 students with humanities background, in a graduate course in the School of Library Service of Columbia University, for elementary mechanized library and documentation tasks. The processor for the larger subset of the language shown in Tables II to V now works, and is being applied to several practical problems. The processor for the full language is being completed. A SNAP procedure consists of a succession of well-formed English sentences of a few simple types. Most of these begin with imperative verbs that are concerned with input and output operations, and with the manipulation of strings of characters, numbers, and arrays of strings and numbers. Conditional sentences begin with IF. Several constructions that extract and concatenate portions of strings and lists of strings are used in the objects of SNAP sentences. The SNAP processor is written (apart from specialized input-output routines) in FORTRAN IV. It deals directly with some 25 "built-in" verbs, and will allow the user to define further verbs by subroutines that are also written in SNAP.

关键词： Natural languages Text processing programming profession Computer aided instruction Libraries Circuits Humans Laboratories Application software Computer applications

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Vision-Based Metal Oxide Semiconductor Transistor-Level Layout Error Classification Using EfficientNet Model

Vision-Based Metal Oxide Semiconductor Transistor-Level Layo...

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2020 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2020

作者： Ilagan, Lorena Concepcion Ii, Ronnie Cabatuan, Melvin Roque, Christian University of Perpetual Help System DALTA Electronics Engineering Department Las Pinãs City Philippines De la Salle University Electronics and Communications Engineering Department Manila Philippines Center for Applied Microelectronics and Programming Inc. Muntinlupa City Philippines

ISBN: (纸本)9781728172019

In response to the emerging challenges of providing intelligent dynamic integrated circuit (IC) layout checking, computer vision in IC design and constraint engineering highlights the opportunities of computational intelligence solutions. In this study, vision-based system architecture is integrated with deep transfer learning models to classify metal oxide semiconductor (MOS) transistor cell-level layout error using one-vs-rest (OvR) multilabel classification. Two layout errors, namely missing contact layer and excess structure around the gate, are generated using the developed tool command language (TCL) script that is executed on Synopsys platform. Missing contact layer error is furtherly subcategorized to metal 1 in place and not fully placed, off positioned contact and its combination. Excess structure around the transistor gate is characterized by excess p-type implant (PIMP) and n-type implant (NIMP) with misaligned diffusion (DIFF) and polysilicon (PO) layers. Feature extraction for MOS-level error classification explored on using MobileNetV2 and EfficientNet variants. It was found that EfficientNetB7 best MobileNetV2 and other variants of EfficientNet in predicting IC layout errors based on nine error subcategories. Hamming loss was found to decrease and inference time to inc.ease as the input image size is inc.eased. The deep transfer network EfficientNetB7 has accuracy of 96.889 %, precision of 88.778 %, recall of 97.444 % and F1score of 91.667 in predicting transistor-level layout errors. Overall, the developed approach in predicting MOS transistor cell-level layout error using integrated computer vision and deep learning proved to be accurate and easy to be replicated for further enhancement to provide advanced layout evaluation. © 2020 IEEE.

关键词： Metals

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Electro-chemical mechanical planarization and its evaluation on BEOL with 65nm node dimensions

Electro-chemical mechanical planarization and its evaluation...

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10th International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference, CMP-MIC 2005

作者： Sakamoto, A. Economikos, L. Ong, P. Naujok, M. Tseng, Wei-Tsu Moon, Y. Salfelder, J. Duboust, A. Nogami, T. Sony Electronics Inc. United States IBM Microelectronics United States AMD Corporation United States Infineon Technologies United States Applied Materials Inc. IBM Semiconductor Research and Development Center United States

A novel copper (Cu) planarization process, Ecmp, integrating electro-chemical mechanical polishing capability on a 300 mm CMP platform with low down force conventional polishing process is being evaluated on 65nm hardware. In the integrated Ecmp process, the bulk Cu is removed by electrochemical mechanical polishing at a high rate. The rate is controlled by applied charge and is independent of down force (0.3psi bulk Cu removal step). The Ecmp process removes topography efficiently and produces a thin planarized Cu film across all pattern densities with a uniform thickness profile across the wafer. A model based electro-chemical removal-profile and an endpoint control across the wafer allows to tune the bulk Cu profile across the wafer. The Cu thickness profile produced by electro-chemical planarization allows the following conventional planarization step to clear remaining Cu with low dishing across the wafer and a careful selection of the barrier slurry allows further fine tuning to enhance overall Ecmp performance. The attributes of electropolish are analyzed. Electrical, defectivity and reliability data on 65nm node using Ecmp for Cu planarization are presented.

关键词： Chemical mechanical polishing

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A 90 nm Static CMOS Technology Gate-Level Integrated Circuit Layout Classification and Error Detection Using EfficientNet Model

A 90 nm Static CMOS Technology Gate-Level Integrated Circuit...

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International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM)

作者： Lorena Ilagan Ronnie Concepcion Melvin Cabatuan Christian Raymund Roque University of Perpetual Help System DALTA Las Piñas City Philippines De La Salle University Manila Philippines Center for Applied Microelectronics and Programming Inc. Muntinlupa Philippines

ISBN: (纸本)9781665429979

Sensitivity issues of the internal design rule check (DRC) capability of an electronic design automation tool are highlighted when the design technology used is not properly configured. However, the integration of computer vision and computational intelligence in the field of constraint engineering and integrated circuit layout has high tendency to resolve this ambiguity. In this study, vision-based architecture is integrated with deep transfer learning network to classify NOT, NAND (no fold and two-finger), and NOR logic gates with 1 μm physical gate polysilicon and 0.5 μ m gate length using 90 nm CMOS technology. Inverter designs with contact (CO) error is generated using missing CO, metal 1 in place and not fully placed, and off positioned CO via an inc.rporated Python-triggered tool command language (TCL) program in the Synopsys platform. EfficientNetB7 perfectly classified NOT and NAND gates, and subcategorized NOT contact error designs. Overall, the developed seamless approach in classifying gate-level integrated circuit design and predicting contact errors using EfficientNetB7 is easy to replicate and can enhance layout assessment.

关键词： Integrated circuit layout Layout Transfer learning Logic gates Tools CMOS technology Integrated circuit modeling

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Vision-Based Metal Oxide Semiconductor Transistor-Level Layout Error Classification Using EfficientNet Model

Vision-Based Metal Oxide Semiconductor Transistor-Level Layo...

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IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

作者： Lorena Ilagan Ronnie Concepcion Melvin Cabatuan Christian Roque University of Perpetual Help System DALTA Las Piñas City Philippines De La Salle University Manila Philippines Center for Applied Microelectronics and Programming Inc. Muntinlupa City Philippines

ISBN: (数字)9781728172026

ISBN: (纸本)9781728172033

关键词： Layout Integrated circuits Feature extraction Integrated circuit modeling Metals Semiconductor device modeling Logic gates

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Ionized-PVD stacked barrier structure of TaN/TaRu for 32nm BEOL integration

Ionized-PVD stacked barrier structure of TaN/TaRu for 32nm B...

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Advanced Metallization Conference 2008, AMC 2008

作者： Nogami, Takeshi Yang, Chih-Chao Rossnagel, Stephen M. Penny, Christopher J. Canaperi, Donald F. Kelly, James J. Flaitz, Philip L. DeHaven, Patrick W. Shaw, Thomas M. Cohen, Stephan A. Hu, Chao-Kun Vo, Tuan A. Zienert, Inka Isobayashi, Atsunobu Chung, Hua Wang, Rongjun Ren, James Seo, Soon-Cheon Rao, Satyavolu S. Papa Simon, Andrew H. Van Der Straten, Oscar Ali, Iqbal Piccirillo, Joe Chiang, Sunny K. Wynne, Jean Spooner, Terry A. Edelstein, Daniel C. IBM Albany Nano Technology Research Center Albany NY 12203 United States IBM T. J. Watson Research Center Yorktown Height NY 10598 United States IBM Microelectronics Center Hopewell Junction NY 12533 United States Advanced Micro Devices Inc. AMD Saxony LLC and Co. KG Germany Toshiba America Electronic Components Inc. Albany NY 12203 United States Applied Materials Inc. Santa Clara CA 95054 United States Applied Materials Inc. Albany Nano Technology Research Center Albany NY 12203 United States

ISBN: (纸本)9781605111254

An ionized-PVD stacked barrier structure of TaN/TaRu was developed for 32nm BEOL integration. The TaN layer serves as a most robust diffusion barrier layer, while the TaRu barrier layer improves wettability of the ionized-PVD Cu seed layer. Observed benefits inc.uded enhanced Cu gap filling performance, resolving a line voiding problem, improvement in electromigration performance, and higher via chain yield than TaN/Ta controls at 32nm BEOL dimension. This stacked barrier structure, which uses two PVD chambers inc.rporating pure Ta and TaRu targets, was proposed based on our material studies showing that neither TaRu nor TaRuN performed adequately alone as Cu and O2/H2O diffusion barriers, but performed well when in conjunction with TaN or TaN/Ta backing layers. The newly proposed TaN/TaRu stacked barrier is a possible solution to extend ionized PVD to 32 nm node BEOL. © 2009 Materials Research Society.

关键词： Copper

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Plasma altered layer model for plasma damage characterization of porous OSG films

Plasma altered layer model for plasma damage characterizatio...

引用

IEEE International Conference on Interconnect Technology

作者： H. Shi H. Huang J. Bao J. Im P. S. Ho Y. Zhou J. T. Pender M. Armacost D. Kyser Microelectronics Research Center University of Texas Austin Austin TX USA Applied Materials Inc. Sunnyvale CA USA

A plasma altered layer model was developed to characterize plasma damage in porous OSG (organosilicate glass) low-k dielectrics by taking into account the kinetics of radical diffusion, reaction, and recombination. A gap structure was designed to study plasma damage and validate the model. It consisted of two parallel rectangular Si spacers and a top optical mask to control the energy and intensity of ion, photon, and radical in the plasma. CO 2 and O 2 plasma-induced damages were found to depend on the radical concentration, the energy and intensity of VUV photons, the ion energy, and the substrate temperature. Overall, the results obtained from plasma damage studies were consistent with the prediction of the model. The application of the model was demonstrated in a study of He plasma pretreatment and damage formation in OSG films with varying carbon concentrations. Both treatments were found to be effective in improving the material resistance to plasma damage.

关键词： Plasma temperature Plasma applications Plasma materials processing Optical control Glass Dielectrics Kinetic theory Spontaneous emission Particle beam optics Optical films

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Mechanistic Study of CO2 Plasma Damage to OSG Low k Dielectrics

Mechanistic Study of CO2 Plasma Damage to OSG Low k Dielectr...

引用

IEEE International Conference on Interconnect Technology

作者： H. Shi J. Bao H. Huang B. Chao S. Smith Y. Sun P. S. Ho A. Li M. Armacost D. Kyser Microelectronics Research Center University of Texas Austin Austin TX USA Applied Perception Inc. Sunnyvale CA USA

A mechanistic study of CO 2 plasma damage to OSG (organosilicate glass) low-k films was performed using both inductive-coupled ICP and capacitive-coupled RIE sources with varying plasma energy and density. The nature of the damage was investigated using spectroscopic ellipsometry (SE), Fourier transform infrared spectroscopy (FTIR), X-ray photoelectron spectrometer (XPS), and capacitance-voltage (C-V) measurements. The spectroscopic data were used to examine the origin of the dielectric loss based on the Kramers-Kronig dispersion relation to follow the change of the polarization components. Upon plasma treatment, the electronic dielectric constant was found to drop first and then rise to reach saturation while the ionic component inc.eased and became saturated. Overall the dipolar contribution was found to dominate the dielectric loss. The extent of CO 2 plasma damage was found to depend on the plasma density, plasma energy and the low k chemistry. Compared with the O 2 plasma, the CO 2 plasma induced less damage probably due to the compensation effect of the carbon in the CO 2 plasma. While the RIE CO 2 plasma induced mostly surface damage, the ICP plasma generated more damage in the bulk of the low k material.

关键词： Plasma density Plasma chemistry Plasma measurements Dielectric losses Plasma materials processing Plasma x-ray sources Plasma sources Spectroscopy Capacitance-voltage characteristics Glass

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CVD Co and its application to Cu damascene interconnections

CVD Co and its application to Cu damascene interconnections

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2010 IEEE International Interconnect Technology Conference, IITC 2010

作者： Nogami, T. Maniscalco, J. Madan, A. Flaitz, P. DeHaven, P. Parks, C. Tai, L. St Lawrence, B. Davis, R. Murphy, R. Shaw, T. Cohen, S. Hu, C.-K. Cabral Jr., C. Chiang, S. Kelly, J. Zaitz, M. Schmatz, J. Choi, S. Tsumura, K. Penny, C. Chen, H.-C. Canaperi, D. Vo, T. Ito, F. Straten, O. Simon, A. Rhee, S.-H. Kim, B.-Y. Bolom, T. Ryan, V. Ma, P. Ren, J. Aubuchon, J. Fine, J. Kozlowski, P. Spooner, T. Edelstein, D. IBM in Albany Nano Science and Technology Research Center IBM Corp. 257 Fuller Road Albany NY 12203 United States IBM T. J. Watson Research Center 1101 Kitchawan Road Route 134 Yorktown Height NY 10598 United States IBM Microelectronics Center 2070 Route 52 Hopewell Junction NY 12533 United States Toshiba America Electronic Components Inc. Albany NY United States Global Foundries Inc. Albany NY United States STMicroelectronics Inc. Hopewell Junction NY United States NEC Electronics Inc. Albany NY United States Applied Materials Inc. Albany NY United States Applied Materials Inc. 3320 Scott Blvd Santa Clara CA 95054 United States

ISBN: (纸本)9781424476763

Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). inc.rporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by AFM) showed correlations with amounts of in-film oxygen/carbon. Cobalt diffused through copper at normal processing temperatures (by SIMS). CVD Co demonstrated diffusion barrier performance to Cu (by Triangular Voltage Sweep, TVS), but not to O2. CVD Co was applied to 32 nm/22 nm damascene Cu interconnect fabrication in a scheme defined by the material studies. Lower post-CMP defect density and longer electromigration lifetimes were obtained. ©2010 IEEE.

关键词： Oxygen

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