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Exploiting Approximation for Run-time Resource Management of embedded HMPs

ACM Transactions on embedded Computing systems 2025年第3期24卷 1-30页

作者： Zain Taufique Anil Kanduri Antonio Miele Amir Rahmani Cristiana Bolchini, PhD Nikil Dutt Pasi Liljeberg Health Technology University of Turku Turku Finland University of Turku Turku Finland DEIB Politecnico di Milano Milano Italy Computer Science University of California Irvine California United States and Institute of Computer Technology Technische Universitat Wien Wien Austria Dip. Elettronica e Informazione Politecnico di Milano Milano Italy Center for Embedded Computer Systems University of California at Irvine Irvine United States IT University of Turku Turku Finland

Run-time resource management (RTM) of multi-programmed workloads on heterogeneous multi-core platforms is challenging due to (i) fixed power budget of the device, (ii) variable performance requirements of the workloads, and (iii) unknown arrival of the applications. Existing RTM solutions lack power-performance coordination, resulting in performance degradation during power actuation or power violations during performance provisioning. Exploiting inherent error-resilience of the applications can address the performance loss incurred in power actuation, by combining run-time approximation with traditional power knobs (including Dynamic Voltage/Frequency Scaling, Task Migration, Degree of Parallelism, and CPU Quota). In this work, we present an accuracy-aware resource management framework that jointly actuates run-time approximation and traditional power knobs for efficient power-performance management of multi-programmed and multi-threaded workloads running on heterogeneous mobile platforms. Our strategy configures the accuracy of the applications at run-time to exploit accuracy-performance trade-offs, by considering system-wide power-performance dynamics. We use heuristic estimation models to jointly enforce accuracy configuration and traditional power knobs settings at run-time. We evaluated our framework on real-world embedded mobile platforms, including Odroid XU3 and Asus Tinker Edge R boards to demonstrate the efficiency of our proposed approach across multiple workload scenarios. Our approach achieved 25% lower performance violations against the state-of-the-art run-time resource management policies at the cost of 2.2% accuracy loss across six applications.

关键词： Run-time mapping DVFS approximation and dynamic power

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Automatic TLM generation for C-based MPSoC design

Automatic TLM generation for C-based MPSoC design

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IEEE International High-Level Design Validation and Test Workshop, HLDVT

作者： Lo, Lucky Chi, Yu Lo Abdi, Samar Center for Embedded Computer Systems UC Irvine CA 92697 United States

ISBN: (纸本)1424414806

This paper presents a tool for automatic generation of transaction level models (TLMs) for MPSoC designs using only C-code and graphical capture. The MPSoC platform is captured as a graphical net-list of components, busses and bridge elements. The application is captured as C processes mapped to the platform components. Once the platform is decided, a set of transaction level communication APIs is automatically generated for each process. After the C code is input, an executable SystemC TLM of the design is automatically generated using our tool. This TLM can be executed using standard SystemC simulators for early functional verification of the design. Although, several TLM styles and standards have been proposed in the past, our approach differs in the fact that the designers do not need to understand the underlying SystemC code or TLM modeling style to verify that their application executes on the selected platform. Moreover, the platform can be easily modified and a new TLM for that platform can be automatically generated. Our experimental results demonstrate that for large industrial applications such as MP3 decoder and H.264, high-speed TLMs can be generated for a wide variety of platforms in a few seconds. ©2007 IEEE.

关键词： Integrated circuit design

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Model based synthesis of embedded software

Journal of Software

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Journal of Software 2009年第7期4卷 717-727页

作者： Abdi, Samar Gajski, Daniel D. Viskic, Ines Center for Embedded Computer Systems University of California Irvine CA 92617 United States

This paper presents software (SW) synthesis using embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore embedded systems based on their platform architecture. We identify key design decisions and models that are required for embedded system synthesis. We present a a model based design methodology that starts with an application model consisting of C processes communicating via abstract message passing channels. The application model is mapped to a platform net-list of SW and hardware (HW) cores, buses and buffers. A high speed Transaction Level Model (TLM) is generated to validate abstract com-munication between processes mapped to different cores. The TLM is further refined into a Pin-Cycle Accurate Model (PCAM) for board implementation. The PCAM includes C code for all the communication layers including routing, packeting, synchronization and bus transfer. The generated embedded SW provides a library of application level services to the C processes on individual SW cores. Therefore, the application developer does not need to write low level SW for board implementation. Synthesis results for multi-core MP3 decoder and JPEG encoder designs, using ESE, show that the embedded SW is generated in order of seconds, compared to hours of manual coding. The quality of synthesized code is comparable to manually written code in terms of performance and code size. Over 3X productivity gain in overall multicore design is shown to result from automatic SW synthesis. © 2009 ACADEMY PUBLISHER.

关键词： embedded systems

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Rapture of the deep

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IEEE Spectrum 2010年第2期47卷 40-41页

作者： Weiss, Giselle Center for Embedded Computer Systems University of California Irvine USA

He makes the dive computer that every aquanaut wants. On one of the last shimmering days of summer, two weathered, middleaged men undress in a parking lot on the northeastern shore of Lake Zurich. This is the city's Gold Coast, where a halfway decent villa will set you back a couple of million francs. Jabbering in a Swiss dialect while working with swift, sure hands, the divers pull on thick black exposure suits and 20 kilograms of gear, including two big steel cylinders of pressurized breathing gas. © 2006 IEEE.

关键词： CHIEF technical officers DIVING DIVING instruction SOFTWARE

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Don't forget memories - A case study redesigning a pattern counting ASIC circuit for FPGAs 08

Don't forget memories - A case study redesigning a pattern c...

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embedded systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

作者： Sheldon, David Vahid, Frank Department of Computer Science and Engineering UC Riverside United States Center for Embedded Computer Systems UC Irvine United States

ISBN: (纸本)9781605584706

Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to speedup performance. Many such circuits have been previously designed for acceleration via application-specific integrated circuits (ASICs). Redesigning an ASIC circuit for FPGA implementation involves several challenges. We describe a case study that highlights a common challenge related to memories. The study involves converting a pattern counting circuit architecture, based on a pipelined binary tree and originally designed for ASIC implementation, into a circuit suitable for FPGAs. The original ASIC-oriented circuit, when mapped to a Spartan 3e FPGA, could process 10 million patterns per second and handle up to 4,096 patterns. The redesigned circuit could instead process 100 million patterns per second and handle up to 32,768 patterns, representing a 10x performance improvement and a 4x utilization improvement. The redesign involved partitioning large memories into smaller ones at the expense of redundant control logic. Through this and other case studies, design patterns may emerge that aid designers in redesigning ASIC circuits for FPGAs as well as in building new high-performance and efficient circuits for FPGAs. Copyright 2008 ACM.

关键词： Application specific integrated circuits

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Highly-cited ideas in system codesign and synthesis 08

Highly-cited ideas in system codesign and synthesis

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embedded systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

作者： Vahid, Frank Givargis, Tony Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems UC Irvine United States Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781605584706

We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/software codesign and system synthesis community. Citations, meaning non-self-citations only, were considered from all papers known to Google Scholar, as well as only from subsequent CODES/ISSS papers. We list the most-cited CODES/ISSS papers of each year, summarizing their topics, and discussing common features of those papers. For comparison purposes, we also measured citations for the computer architecture community's ISCA and MICRO conferences, and for the field-programmable gate array community's FPGA and FCCM conferences. We point out several interesting differences among the citation patterns of the three communities. Copyright 2008 ACM.

关键词： computer architecture

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Energy-efficient design for highly associative instruction caches in next-generation embedded processors

Energy-efficient design for highly associative instruction c...

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Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04

作者： Aragon, Juan Luis Nicolaescu, Dan Veidenbaum, Alex Badulescu, Ana-Maria Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)0769520855

This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructions in a given I-cache fetch are used due to branches. The proposed predictor determines which instructions in a cache access will be used and does not fetch any other instructions. Results show an average I-cache energy savings of 44% over the baseline case and 6% over the segmented case with no negative impact on performance.

关键词： Microprocessor chips

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A first look at the interplay of code reordering and configurable caches

A first look at the interplay of code reordering and configu...

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2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05

作者： Gordon-Ross, Ann Vahid, Frank Dutt, Nikil Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems School of Information and Computer Science University of California Irvine United States Center for Embedded Computer Systems UC Irvine United States

The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache's high impact on system performance and power, and because of the cache's predictable temporal and spatial locality. Optimization techniques can be designed based on this predictability. We explore for the first time the interplay of two popular instruction cache optimization techniques: the long-known technique of code reordering and the relatively-new technique of cache configuration. We address the question of whether those two optimizations complement each other or if one optimization dominates the other. Through experiments using embedded system benchmarks, we show that cache configuration dominates a particular category of code reordering techniques with respect to optimizing performance and energy, obviating the need for reordering. We also examine the modern scenario of synthesized custom caches, and show that combining cache configuration with code reordering results in cache size reductions of 13% on average, and up to 89% in some benchmarks, beyond just cache configuration alone. Copyright 2005 ACM.

关键词： Buffer storage

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A simplified java bytecode compilation system for resource-constrained embedded processors

A simplified java bytecode compilation system for resource-c...

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CASES'07: 2007 International Conference on Compilers, Architecture, and Synthesis for embedded systems

作者： Badea, Carmen Nicolau, Alexandru Veidenbaum, Alexander V. Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)9781595938268

embedded platforms are resource-constrained systems in whichperformance and memory requirements of executed code are ofcritical importance. However, standard techniques such as full just-in-time(JIT) compilation and/or adaptive optimization (AO) may not be appropriate for this type of systems due to memory and compilation overheads. The research presented in this paper proposes a technique that combines some of the main benefits of JIT compilation, superoperators(SOs) and profile-guided optimization, in order to deliver a lightweight Java bytecode compilation system, targeted for resource-constrained environments, that achieves runtime performance similar to that of state-of-the-art JIT/AO systems, while having a minimal impact on runtime memory *** key ideas are to use profiler-selected, extended bytecode basic blocks as superoperators (new bytecode instructions) and to perform few, but very targeted, JIT/AO-like optimizations at compile time only on the superoperators. bytecode, as directed by compilation .hints. encoded as annotations. As such, our system achieves competitive performance to a JIT/AO system, but witha much lower impact on runtime memory consumption. Moreover,it is shown that our proposed system can further improveprogram performance by selectively inlining method calls embedded in the chosen superoperators, as directed by runtime profiling data and with minimal impact on classfile size. For experimental evaluation, we developed three Virtual Machines(VMs) that employ the ideas presented above. The customized VMs are first compared (w.r.t. runtime performance) to a simple, fast-to-develop VM (baseline) and then to a VM that employs JIT/AO. Our best-performing system attains speedups ranging from a factor of 1.52 to a factor of 3.07, w.r.t. to the baseline VM. When compared to a state-of-the-art JIT/AO VM, our proposed system performs better for three of the benchmarks and worse by less than a factor of 2 for three others. But our SO-ext

关键词： embedded systems

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Generic netlist representation for system and PE level design exploration

Generic netlist representation for system and PE level desig...

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CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Gorjiara, Bita Reshadi, Mehrdad Chandraiah, Pramod Gajski, Daniel Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)1595933700

Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems require more productive design approaches starting from high-level languages such as C. On the other hand, tight constraints of embedded systems require careful design exploration at system level (coarse grained exploration) and at the processing-element (PE) level (fine grained exploration).In this paper we presented GNR, a formal modeling approach, developed to improve productivity of designing systems and processing elements, the same way that traditional ADLs improved productivity for designing processors. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. Using relatively short GNR description, we explored several designs for implementing an MP3 decoder and achieved 3.25 speedup compared to MicroBlaze processor. We have also developed a web-based interface for our tools, so that users can upload and evaluate new architectures described in GNR. Our toolset and GNR is an intermediate step towards synthesis of TLM to RTL. © Copyright 2006 ACM.

关键词： systems analysis

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