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15th International Symposium on System Synthesis

作者： Gerstlauer, Andreas Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine Irvine CA 92697-3425 United States

Raising the level of abstraction is widely seen as the solution for closing the productivity gap in system design. They key for the success of this approach, however, are well-defined abstraction levels and models. In this paper, we present such system level semantics to cover the system design process. We define properties and features of each model. Formalization of the flow enables design automation for synthesis and verification to achieve the required productivity gains. Through customization, the semantics allow creation of specific design methodologies. We applied the concepts to system languages SystemC and SpecC. Using the example of a JPEG encoder, we will demonstrate the feasibility and effectiveness of the approach.

关键词： systems analysis

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computer-aided recoding to create structured and analyzable system models

Computer-aided recoding to create structured and analyzable ...

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作者： Chandraiah, Pramod Dömer, Rainer Center for Embedded Computer Systems University of California at Irvine Irvine CA 92697-2625 United States

In embedded system design, the quality of the input model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-written system model, tools today are effective in generating working implementations. However, readily available C reference code is not conducive for immediate system synthesis as it lacks needed features for automatic analysis and synthesis. Among others, the lack of proper structure and the presence of intractable pointers in the reference code are factors that seriously hamper the effectiveness of system design tools. To overcome these deficiencies, we aim to automate the conversion of flat C code into a well-structured system model by applying automated source code transformations. We present a set of computer-aided recoding operations that enable the system designer to mitigate pointer problems and quickly create the necessary structural hierarchy so that the design model becomes easily analyzable and synthesizable. Utilizing the designer's knowledge, our interactive recoding transformations aid the designer in efficiently creating well-structured system models for rapid design space exploration and successful synthesis. Our estimated and measured experimental results show significant productivity gains through a substantial reduction of the model creation time. © 2012 ACM.

关键词： embedded systems

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Processor-Memory Coexploration Using an Architecture Description Language

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ACM Transactions on embedded Computing systems 2004年第1期3卷 140-162页

作者： Mishra, Prabhat Mamidipaka, Mahesh Dutt, Nikil Center for Embedded Computer Systems 444 Computer Science University of California Irvine CA 92697-3430 United States

Memory represents a major bottleneck in modern embedded systems in terms of cost, power, and performance. Traditionally, memory organizations for programmable embedded systems assume a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for specific target applications. However, such a processor-memory coexploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem configuration, generate a memory-aware software toolkit, and perform coexploration of the processor-memory architectures. We present a set of experiments using our memory-aware architectural description language (ADL) to drive the exploration of the memory subsystem for the TI C6211 processor architecture, demonstrating cost, performance, and energy trade-offs. © 2004, ACM. All rights reserved.

关键词： architecture description language Design design space exploration Experimentation Languages memory exploration Processor-memory codesign

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EmPro: An environment/energy emulation and profiling platform for wireless sensor networks

EmPro: An environment/energy emulation and profiling platfor...

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2006 3rd Annual IEEE Communications Society on Sensor and Ad hoc Communications and Networks, Secon 2006

作者： Park, Chulsung Chou, Pai H. Center for Embedded Computer Systems University of California Irvine Irvine CA 92697-2625 United States

ISBN: (纸本)1424406269

Quantitative evaluation of wireless sensor platforms is difficult. Unlike general purpose computers that can run SPEC benchmarks from a file, it is difficult to reproduce the environmental input needed to stimulate the sensor nodes. Even if possible, open-loop playback would be unable to correctly account for adaptivity built into the behavior of these nodes. As a result, researchers resort to simulations, which do not consider all relevant factors without significant speed penalty. To address this problem, we propose EmPro, an environment/energy emulation and profiling system for WSNs. It accurately outputs electrical signals to emulate not only digital and analog inputs to the sensors but also the power sources as well as RF attenuation according to pre-programmed sequences. This emulation approach enables researchers to run the networked sensors in real-time in a realistic manner with full controllability and reproducibility. EmPro in profiling mode can also capture the observable behavior of WSNs for detailed analysis. Experimental results on the Eco and MICA2 WSN platforms show that EmPro can drive these hardware systems in real-time with high accuracy. We expect EmPro will expedite testing and serve as a sorely needed standard benchmarking tool for WSN platforms. © 2006 IEEE.

关键词： Wireless sensor networks

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Cryptic primes

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IEEE Potentials 2004年第1期23卷 43-45页

作者： Kejariwal, Arun Center for Embedded Computing Systems University of California Irvine United States IEEE United States IEEE Computer Society United States

No abstract available

关键词： Public key Public key cryptography Internet Security Computational complexity Equations Transmitters

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Automatic generation of transaction level models for rapid design space exploration

Automatic generation of transaction level models for rapid d...

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CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Shin, Dongwan Gerstlauer, Andreas Peng, Junyu Dömer, Rainer Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine CA 92697 United States

ISBN: (纸本)1595933700

Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer's productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space. © Copyright 2006 ACM.

关键词： Logic design

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Automatic generation of bus functional models from transaction level models

Automatic generation of bus functional models from transacti...

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Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004

作者： Shin, Dongwan Abdi, Samar Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine CA 92697 United States

This paper presents methodology and algorithms for generating bus functional models from transaction level models in system level design. Transaction level models are often used by designers for prototyping the bus functional architecture of the system. Being at a higher level of abstraction gives transaction level models the unique advantage of high simulation speed. This means that the designer can explore several bus functional architectures before choosing the optimal one. However, the process of converting a transaction level model to a bus functional model is not trivial. A manual conversion would not only be time consuming but also error prone. A bus functional model should also accurately represent the corresponding transaction level model. We present algorithms for automating this refinement process. Experimantal results presented using a tool based on these algorithms show their usefulness and feasibility.

关键词： computer systems

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Energy aware task scheduling with task synchronization for embedded real time systems

Energy aware task scheduling with task synchronization for e...

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2002 International Conference on Compilers, Architecture, and Synthesis for embedded systems, CASES '02

作者： Jejurikar, Ravindra Gupta, Rajesh Center for Embedded Computer Systems Department of Information and Computer Science University of California at Irvine Irvine CA 92697 United States

ISBN: (纸本)1581135750

Slowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic Voltage Scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings. The problem of DVS in the presence of task synchronization has not yet been addressed. We compute slowdown factors for tasks which synchronize for access to shared resources. Tasks synchronize to enforce mutually exclusive access to these resources and can be blocked by lower priority tasks. We compute static slowdown factors for the tasks which guarantee meeting all the task deadlines. Our simulation experiments show on an average 25% energy gains over the known slowdown techniques. Copyright 2002 ACM.

关键词： Voltage scaling

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Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations 11

Reliability-aware placement in SRAM-based FPGA for voltage s...

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embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM International Conference on Hardware/Software-Codesign and System Synthesis, CODES+ISSS'11

作者： Golshan, Shahin Khajeh, Amin Homayoun, Houman Bozorgzadeh, Eli Eltawil, Ahmed Kurdahi, Fadi J. Center of Embedded Computer Systems University of California Irvine CA 92697 United States

ISBN: (纸本)9781450307154

With advances in technology scaling, the configuration memory in SRAM-based FPGA is contributing a large portion of power consumption. Voltage scaling has been widely used to address the increases in power consumption in submicron regimes. However, with the advent of process variation in the configuration SRAMs, voltage scaling can undermine the integrity of a design implemented on the FPGA device as the design's functionality is determined by the contents of the configuration SRAMs. In this paper, we propose to exploit the abundance of homogenous resources on FPGA, in order to realize voltage scaling in the presence of process variation. Depending on the design to be implemented on FPGA, we select the minimal voltage that sustains a reliable placement. We then introduce a novel 2-phase placement algorithm that maximizes the reliability of the implemented design when voltage scaling is applied to the configuration memory. In the first phase, pre-deployment placement, we maximize the reliability of the implemented designs considering the a priori distribution of SRAM failures due to process variation and voltage scaling. The second phase, post-deployment placement, is performed once the device is fabricated in order to determine a fault-free placement of the design for the FPGA device. Our results indicate significant leakage power reduction (more than 50%) in the configuration memory when our placement technique is combined with voltage scaling with little delay degradation. Copyright 2011 ACM.

关键词： computer aided design

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Automatic model refinement for fast architecture exploration [SoC design] 7

Automatic model refinement for fast architecture exploration...

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7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

作者： Peng, J. Abdi, S. Gajski, D. Center for Embedded Computer Systems University of California IrvineCA92697 United States

ISBN: (纸本)0769514413

We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An architecture model is derived from the specification through a series of well defined steps in our design methodology. Traditional architecture exploration relies on manual refinement which is painfully time consuming and error prone. The automation of the refinement process provides a useful tool to the system designer to quickly evaluate several architectures in the design space and make the optimal choice. Experiments with the tool on a system design example show the robustness and usefulness of the refinement algorithm. © 2002 IEEE.

关键词： System-on-chip

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