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20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Seo, Sangmin Kim, Junghyun Lee, Jaejin Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul 151-744 Korea Republic of

ISBN: (纸本)9780769545660

As parallel programming becomes the mainstream due to multicore processors, dynamic memory allocators used in C and C++ can suppress the performance of multi-threaded applications if they are not scalable. In this paper, we present a new dynamic memory allocator for multi-threaded applications. The allocator never uses any synchronization for common cases. It uses only lock-free synchronization mechanisms for uncommon cases. Each thread owns a private heap and handles memory requests on the heap. Our allocator is completely synchronization-free when a thread allocates a memory block and deallocates it by itself. Synchronization-free means that threads do not communicate with each other at all. On the other hand, if a thread allocates a block and another thread frees it, we use a lock-free stack to atomically add it to the owner thread's heap to avoid the memory blowup problem. Furthermore, our allocator exploits various memory block caching mechanisms to reduce the latency of memory management. Freed blocks or intermediate memory chunks are cached hierarchically in each thread's heap and they are used for future memory allocation. We compare the performance and scalability of our allocator to those of well-known existing multi-threaded memory allocators using eight benchmarks. Experimental results on a 48-core AMD system show that our approach achieves better performance than other allocators for all benchmarks and is highly scalable with a large number of threads. © 2011 IEEE.

关键词： Synchronization

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OpenCL as a programming model for GPU clusters

OpenCL as a programming model for GPU clusters

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24th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2011

作者： Kim, Jungwon Seo, Sangmin Lee, Jun Nah, Jeongho Jo, Gangwon Lee, Jaejin Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul 151-744 Korea Republic of

ISBN: (纸本)9783642360350

In this paper, we propose an OpenCL framework for GPU clusters. The target cluster architecture consists of a single host node and multiple compute nodes. They are connected by an interconnection network, such as Gigabit and InfiniBand switches. Each compute node consists of multiple GPUs. Each GPU becomes an OpenCL compute device. The host node executes the host program in an OpenCL application. Our OpenCL framework provides an illusion of a single system for the user. It allows the application to utilize GPUs in a compute node as if they were in the host node. No communication API, such as the MPI library, is required in the application source. We show that the original OpenCL semantics naturally fits to the GPU cluster environment, and the framework achieves both high performance and ease of programming. We implement the OpenCL framework and evaluate its performance on a GPU cluster that consists of one host and eight compute nodes using six OpenCL benchmark applications. © 2013 Springer-Verlag.

关键词： Graphics processing unit

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SnuCL: An OpenCL framework for heterogeneous CPU/GPU clusters 12

SnuCL: An OpenCL framework for heterogeneous CPU/GPU cluster...

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26th ACM International Conference on Supercomputing, ICS'12

ISBN: (纸本)9781450313162

In this paper, we propose SnuCL, an OpenCL framework for heterogeneous CPU/GPU clusters. We show that the original OpenCL semantics naturally fits to the heterogeneous cluster programming environment, and the framework achieves high performance and ease of programming. The target cluster architecture consists of a designated, single host node and many compute nodes. They are connected by an interconnection network, such as Gigabit Ethernet and InfiniBand switches. Each compute node is equipped with multicore CPUs and multiple GPUs. A set of CPU cores or each GPU becomes an OpenCL compute device. The host node executes the host program in an OpenCL application. SnuCL provides a system image running a single operating system instance for heterogeneous CPU/GPU clusters to the user. It allows the application to utilize compute devices in a compute node as if they were in the host node. No communication API, such as the MPI library, is required in the application source. SnuCL also provides collective communication extensions to OpenCL to facilitate manipulating memory objects. With SnuCL, an OpenCL application becomes portable not only between heterogeneous devices in a single node, but also between compute devices in the cluster environment. We implement SnuCL and evaluate its performance using eleven OpenCL benchmark applications. Copyright 2012 ACM.

关键词： Program processors

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A software-managed coherent memory architecture for manycores

A software-managed coherent memory architecture for manycore...

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20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Park, Jungho Jang, Choonki Lee, Jaejin Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul 151-744 Korea Republic of

ISBN: (纸本)9780769545660

Cache coherent Non-Uniform Memory Access (cc-NUMA) architectures have been widely used for chip multiprocessors (CMPs). However, they require complicated hardware to properly handle the cache coherence problem. Moreover, it generates heavy on-chip network traffic due to the coherence enforcement. In this work, we propose a simple software-managed coherent memory architecture for manycores. Our memory architecture exploits explicitly addressed local stores. Instead of implementing the complicated cache coherence protocol in hardware, coherence and consistency are supported by software, such as a runtime or an operating system. The local stores together with the software leverage conventional caches to make the architecture much simpler and to generate much less network traffic than conventional ccNUMA-based CMPs. Experimental results indicate that our approach is promising. © 2011 IEEE.

关键词： Memory architecture

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An OpenCL framework for homogeneous manycores with no hardware cache coherence

An OpenCL framework for homogeneous manycores with no hardwa...

引用

20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Lee, Jun Kim, Jungwon Kim, Junghyun Seo, Sangmin Lee, Jaejin Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul 151-744 Korea Republic of

ISBN: (纸本)9780769545660

Recently, Intel has introduced a research prototype manycore processor called the Single-chip Cloud Computer (SCC). The SCC is an experimental processor created by Intel Labs. It contains 48 cores in a single chip and each core has its own L1 and L2 caches without any hardware support for cache coherence. It allows maximum 64GB size of external memory that can be accessed by all cores and each core dynamically maps the external memory into their own address space. In this paper, we introduce the design and implementation of an OpenCL framework (i.e., runtime and compiler) for such manycore architectures with no hardware cache coherence. We have found that the OpenCL coherence and consistency model fits well with the SCC architecture. The OpenCL's weak memory consistency model requires relatively small amount of messages and coherence actions to guarantee coherence and consistency between the memory blocks in the SCC. The dynamic memory mapping mechanism enables our framework to preserve the semantics of the buffer object operations in OpenCL with a small *** have implemented the proposed OpenCL runtime and compiler and evaluate their performance on the SCC with OpenCL applications. © 2011 IEEE.

关键词： Semantics

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CyCNN: A Rotation Invariant CNN Using Polar Mapping and Cylindrical Convolution Layers

arXiv

引用

arXiv 2020年

作者： Kim, Jinpyo Jung, Wookeun Kim, Hyungmo Lee, Jaejin Center for Manycore Programming Seoul National University Seoul Korea Republic of

Deep Convolutional Neural Networks (CNNs) are empirically known to be invariant to moderate translation but not to rotation in image classification. This paper proposes a deep CNN model, called CyCNN, which exploits polar mapping of input images to convert rotation to translation. To deal with the cylindrical property of the polar coordinates, we replace convolution layers in conventional CNNs to cylindrical convolutional (CyConv) layers. A CyConv layer exploits the cylindrically sliding windows (CSW) mechanism that vertically extends the input-image receptive fields of boundary units in a convolutional layer. We evaluate CyCNN and conventional CNN models for classification tasks on rotated MNIST, CIFAR-10, and SVHN datasets. We show that if there is no data augmentation during training, CyCNN significantly improves classification accuracies when compared to conventional CNN models. Our implementation of CyCNN is publicly available on https://***/mcrl/CyCNN Copyright © 2020, The Authors. All rights reserved.

关键词： Convolution

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MAPA: An Automatic Memory Access Pattern Analyzer for GPU Applications

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ACM SIGPLAN Notices 2017年第8期52卷 443-444页

作者： Jo, Gangwon Jung, Jaehoon Park, Jiyoung Lee, Jaejin Center for Manycore Programming Department of Computer Science and Engineering Seoul National University Seoul08826 Korea Republic of

Various existing optimization and memory consistency management techniques for GPU applications rely on memory access patterns of kernels. However, they suffer from poor practicality because they require explicit user interventions to extract kernel memory access patterns. This paper proposes an automatic memory-access-pattern analysis framework called MAPA. MAPA is based on a source-level analysis technique derived from traditional symbolic analyses and a run-time pattern selection technique. The experimental results show that MAPA properly analyzes 116 real-world OpenCL kernels from Rodinia and Parboil. © 2017 ACM.

关键词： Graphics processing unit

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PIPSEA: A practical IPsec gateway on embedded APUs 16

PIPSEA: A practical IPsec gateway on embedded APUs

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23rd ACM Conference on Computer and Communications Security, CCS 2016

作者： Park, Jungho Jung, Wookeun Jo, Gangwon Lee, Ilkoo Lee, Jaejin Center for Manycore Programming Department of Computer Science and Engineering Seoul National University Seoul08826 Korea Republic of ManyCoreSoft Co. Ltd. Building 138 Seoul National University Seoul08826 Korea Republic of

ISBN: (纸本)9781450341394

Accelerated Processing Unit (APU) is a heterogeneous multicore processor that contains general-purpose CPU cores and a GPU in a single chip. It also supports Heterogeneous System Architecture (HSA) that provides coherent physically-shared memory between the CPU and the GPU. In this paper, we present the design and implementation of a high-performance IPsec gateway using a low-cost commodity embedded APU. The HSA supported by the APUs eliminates the data copy overhead between the CPU and the GPU, which is unavoidable in the previous discrete GPU approaches. The gateway is implemented in OpenCL to exploit the GPU and uses zero-copy packet I/O APIs in DPDK. The IPsec gateway handles the real-world network traffic where each packet has a different workload. The proposed packet scheduling algorithm significantly improves GPU utilization for such traffic. It works not only for APUs but also for discrete GPUs. With three CPU cores and one GPU in the APU, the IPsec gateway achieves a throughput of 10.36 Gbps with an average latency of 2.79 ms to perform AESCBC+ HMAC-SHA1 for incoming packets of 1024 bytes. © 2016 ACM.

关键词： Graphics processing unit

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An OpenCL Framework for Homogeneous manycores with No Hardware Cache Coherence

An OpenCL Framework for Homogeneous Manycores with No Hardwa...

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International Conference on Parallel Architecture and Compilation Techniques (PACT)

作者： Jun Lee Jungwon Kim Junghyun Kim Sangmin Seo Jaejin Lee Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul South Korea

Recently, Intel has introduced a research prototype many core processor called the Single-chip Cloud Computer (SCC). The SCC is an experimental processor created by Intel Labs. It contains 48 cores in a single chip and each core has its own L1 and L2 caches without any hardware support for cache coherence. It allows maximum 64GB size of external memory that can be accessed by all cores and each core dynamically maps the external memory into their own address space. In this paper, we introduce the design and implementation of an OpenCL framework (i.e., runtime and compiler) for such many core architectures with no hardware cache coherence. We have found that the OpenCL coherence and consistency model fits well with the SCC architecture. The OpenCL's weak memory consistency model requires relatively small amount of messages and coherence actions to guarantee coherence and consistency between the memory blocks in the SCC. The dynamic memory mapping mechanism enables our framework to preserve the semantics of the buffer object operations in OpenCL with a small overhead. We have implemented the proposed OpenCL runtime and compiler and evaluate their performance on the SCC with OpenCL applications.

关键词： Kernel Runtime Coherence Indexes Arrays Copper

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Performance characterization of the NAS Parallel Benchmarks in OpenCL

Performance characterization of the NAS Parallel Benchmarks ...

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IEEE International Workshop/Symposium on Workload Characterization

作者： Sangmin Seo Gangwon Jo Jaejin Lee Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul South Korea

Heterogeneous parallel computing platforms, which are composed of different processors (e.g., CPUs, GPUs, FPGAs, and DSPs), are widening their user base in all computing domains. With this trend, parallel programming models need to achieve portability across different processors as well as high performance with reasonable programming effort. OpenCL (Open Computing Language) is an open standard and emerging parallel programming model to write parallel applications for such heterogeneous platforms. In this paper, we characterize the performance of an OpenCL implementation of the NAS Parallel Benchmark suite (NPB) on a heterogeneous parallel platform that consists of general-purpose CPUs and a GPU. We believe that understanding the performance characteristics of conventional workloads, such as the NPB, with an emerging programming model (i.e., OpenCL) is important for developers and researchers to adopt the programming model. We also compare the performance of the NPB in OpenCL to that of the OpenMP version. We describe the process of implementing the NPB in OpenCL and optimizations applied in our implementation. Experimental results and analysis show that the OpenCL version has different characteristics from the OpenMP version on multicore CPUs and exhibits different performance characteristics depending on different OpenCL compute devices. The results also indicate that the application needs to be rewritten or re-optimized for better performance on a different compute device although OpenCL provides source-code portability.

关键词： Kernel Graphics processing unit Multicore processing Indexes Computational modeling Optimization

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