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An enhanced parallel loop self-scheduling scheme for cluster environments

An enhanced parallel loop self-scheduling scheme for cluster...

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19th International Conference on Advanced Information Networking and Applications, AINA 2005

作者： Yang, Chao-Tung Cheng, Kuan-Wei Li, Kuan-Ching High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung City 40704 Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung County 43301 Taiwan

ISBN: (纸本)0769522491

In this paper, a parallel loop self-scheduling scheme for heterogeneous PC cluster systems is proposed. Though the proposed scheme does allow users to choose parameters before the execution initialization phase, there are still weaknesses that motivate us to go further with new improvements in that scheme. For instance, a decision on a fixed and monotonous parameter can easily lead to invalid schedule by using previous input information. Thus, it is proposed in this paper a new scheme, where the scheduling parameter can be adjusted dynamically and fit into most widely available computer systems, in order to provide higher overall performance. © 2005 IEEE.

关键词： Scheduling

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A high-performance computational resource broker for Grid computing environments

A high-performance computational resource broker for Grid Co...

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19th International Conference on Advanced Information Networking and Applications, AINA 2005

作者： Yang, Chao-Tung Shih, Po-Chi Li, Kuan-Ching High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung City 40704 Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung County 43301 Taiwan

ISBN: (纸本)0769522491

Internet computing and grid technologies promise to change the way we tackle complex problems. They will enable large-scale aggregation and sharing of computational, data and other resources across institutional boundaries. As Grid computing is becoming a reality, there is a need for managing and monitoring the available resources worldwide, ax well as the need for conveying these resources to the everyday user. This paper describes a resource broker with its main function as to match the available resources to the user's needs. The use of the resource broker provides a uniform interface to access any of the available and appropriate resources using user's credentials. The resource broker runs on top of the Globus Toolkit. Therefore, it provides security and current information about the available resources and serves as a link to the diverse systems available in the Grid. © 2005 IEEE.

关键词： Computer systems

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Asynchronous parallel algorithms for test set partitioned fault simulation

Asynchronous parallel algorithms for test set partitioned fa...

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Workshop on Principles of Advanced and distributed Simulation (PADS)

作者： D. Krishnaswamy P. Banerjee E.M. Rudnick J.H. Patel Center for Reliable and High Performance Computing University of Illinois Urbana IL USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

We propose two new asynchronous parallel algorithms for test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors. These algorithms provide the same result as the previous synchronous two stage approach. However, due to the dynamic characteristics of these algorithms and due to the fact that there is very minimal redundant work, they run faster than the previous synchronous approach. A theoretical analysis comparing the various algorithms is also given to provide an insight into these algorithms. The implementations were done in MPI and are therefore portable to many parallel platforms. Results are shown for a shared memory multiprocessor.

关键词： parallel algorithms Circuit faults Circuit simulation Partitioning algorithms Circuit testing Computational modeling Sequential circuits Semiconductor device testing distributed computing Algorithm design and analysis

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Evaluation of compiler and runtime library approaches for supporting parallel regular applications

Evaluation of compiler and runtime library approaches for su...

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International Symposium on parallel Processing

作者： D.R. Chakrabarti P. Banerjee A. Lain Center for Parallel and Distributed Computing Northwestern University Evanston IL USA Hewlett-Packard Laboratoties Barcelona Spain

Important applications including those in computational chemistry, computational fluid dynamics, structural analysis and sparse matrix applications usually consist of a mixture of regular and irregular accesses. While current state-of-the-art run-time library support for such applications handles the irregular accesses reasonably well, the efficacy of the optimizations at run-time for the regular accesses is yet to be proven. This paper aims to find a better approach to handle the above applications in a unified compiler and run-time framework. Specifically, this paper considers only regular applications and evaluates the performance of two approaches, a run-rime approach using PILAR and a compile-time approach using a commercial HPF compiler. This study shows that using a particular representation of regular accesses, the performance of regular code using run-time libraries can come close to the performance of code generated by a compiler. It also determines the operations that usually contribute largely to the run-time overhead in case of regular accesses. Experimental results are reported for three regular applications on a 16-processor IBM SP-2.

关键词： Runtime library Concurrent computing Computational fluid dynamics High performance computing Program processors Programming profession Standards development Contracts Optimizing compilers Costs

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On the complexity of learning with a small number of nodes

On the complexity of learning with a small number of nodes

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International Joint Conference on Neural Networks (IJCNN)

作者： I. Parberry Center for Research in Parallel and Distributed Computing Department of Computer Sciences University of North Texas Denton TX USA

It is shown that the loading problem for a six-node neural network with a node function set AC/sub 10/, i.e., the conjunction or disjunction of a subset of the inputs or their complements is NP complete. It can be deduced from this observation that the loading problem for a six-node analog neural network is NP hard. The loading problem for a four-node neural network with a node function set equal to AC/sub 10/ plus the three-input equality function is shown to be NP complete, and it is indicated how the required results can be derived in a similar fashion. Three loading problems are studied.< >

关键词： Neural networks Computer architecture distributed computing Computer networks Boolean functions Concurrent computing Page description languages Electronic mail

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Dynamic load balancing strategies for conservative parallel simulations

Dynamic load balancing strategies for conservative parallel ...

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Workshop on Principles of Advanced and distributed Simulation (PADS)

作者： A. Boukerche S.K. Das Center for Research in Parallel and Distributed Computing Department of Computer Science University of North Texas Denton TX USA

This paper studies the problem of load balancing for conservative parallel simulations for execution on a multicomputer. The synchronization protocol makes use of Chandy-Misra (1979) null-messages. We propose a dynamic load balancing algorithm which assumes no compile time knowledge about the workload parameters. It is based upon a process migration mechanism, and the notion of CPU-queue length, which indicates the workload at each processor. We examine two variations for the algorithm which we refer to as centralized and multi-level hierarchical methods, in the context of queueing network simulation of a torus. The torus was chosen because its many cycles aid in the formation of deadlock, making it a stress test for any conservative synchronization protocols. Our experiments indicate that our dynamic load balancing schemes significantly reduce the run time of an optimized version of Chandy-Misra null message approach, and decreases by 30-40% the synchronization overhead when compared to the use of a static partitioning algorithm. Significantly, the results obtained also indicate that the multi-level scheme always outperforms both the centralized load balancing approach and the static partitioning algorithm.

关键词： Load management Computational modeling Protocols distributed computing Stress Testing Partitioning algorithms Discrete event simulation Computer simulation Concurrent computing

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Cost-optimal parallel algorithms for finitely inductive sequences

Cost-optimal parallel algorithms for finitely inductive sequ...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： S.K. Das P.S. Fisher H. Zhang Center for Research in Parallel and Distributed Computing Department of Computer Science University of North Texas Denton TX USA

Finitely inductive (FI) sequences are a class of sequences, finite or infinite, which are amenable to a certain mathematical representation which has direct significance to pattern recognition and string matching. The authors propose cost-optimal parallel algorithms for FI sequence processing. These algorithms include parallel factoring and following by bucket packing and by hashing on an exclusive-read and exclusive-write (EREW), parallel random access machine (PRAM) model. Each of the algorithms achieves cost-optimal speedup under certain conditions as detailed.< >

关键词： parallel algorithms Pattern recognition Pattern matching distributed computing Computer science Impedance matching Phase change random access memory Multiple signal classification Signal detection Motion detection

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Simultaneous scheduling, binding and floorplanning in high-level synthesis

Simultaneous scheduling, binding and floorplanning in high-l...

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International Conference on VLSI Design

作者： P. Prabhakaran P. Banerjee Center for Reliable and High peerformance Computing University of Illinois Urbana IL USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

With small device features in sub-micron technologies, interconnection delays play a dominant part in cycle time. Therefore, it is important to consider the impact of physical design during high level synthesis. In this paper, an efficient floorplanning algorithm which takes into account the effect of interconnect delays on the overall cycle time of a given schedule is presented. A simultaneous scheduling, binding and floorplanning algorithm is also presented. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower latency and area. In addition, a detailed model is considered, taking into account multiplexer and register areas and delays.

关键词： High level synthesis Delay effects Scheduling algorithm Simulated annealing Processor scheduling Algorithm design and analysis Flow graphs Contracts distributed computing Registers

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Cost-optimal parallel algorithms for traversing trees

Cost-optimal parallel algorithms for traversing trees

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IEEE Southeastcon

作者： S.K. Das C.C.-Y. Chen Center of Research in Parallel and Distributed Computing Department of Computer Science University of North Texas Denton TX USA

The authors present cost-optimal parallel algorithms for depth-order (e.g., pre-, in-, and post-order) and level-order (e.g., breadth-first and breadth-depth) traversals of general trees with n nodes. Each of the algo... 详细信息

关键词： parallel algorithms Phase change random access memory Computer science Binary trees distributed computing Classification tree analysis Algorithm design and analysis

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Integrating task and data parallelism in an irregular application: a case study

Integrating task and data parallelism in an irregular applic...

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International Symposium on parallel and distributed Processing (IPDPS)

作者： K. McPherson P. Banerjee Cyrix Corporation Richardson TX USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

Recently, there has been growing interest in simultaneous exploitation of task and data parallelism in scientific applications and in compiler and runtime support of this combined form of parallelism. In this paper we report on the integration of task and data parallelism on an important irregular application from the VLSI computer-aided design field, namely VLSI layout verification. We report on the implementation, and experimental results of our study on a SUN Sparcserver 1000 shared memory multiprocessor, a CM-5 distributed memory multiprocessor.

关键词： Computer aided software engineering parallel processing Very large scale integration Runtime Application software Concurrent computing Data structures Algorithm design and analysis distributed computing Sun

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