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International Symposium on parallel Processing

作者： D.R. Chakrabarti P. Banerjee Center for Parallel and Distributed Computing ECE Department Tech.Institute Northwestern University Evanston IL USA

This paper explains how efficient support for semi-regular distributions can be incorporated in a uniform compilation framework for hybrid applications. The key focus of this work is in showing how, unlike other existing schemes, our scheme is able to minimize preprocessing overheads and maintain sophisticated communication optimizations (such as reduction of inter-processor communication during schedule generation and sharing of communicated information between regular and irregular accesses) even in the presence of semi-regular distributions. It is only natural that preprocessing overheads associated with semi-regular distributions be intermediate between those involved for regular and irregular distributions. This paper shows how various properties can be inferred for semi-regular distributions. These allow the use of the interval representation which in turn reduces the preprocessing overhead and makes possible compatible code generation for hybrid references. Experimental results on a 16-processor IBM SP-2 for a number of sparse applications using semi-regular distributions show that our scheme is feasible.

关键词： Sparse matrices Runtime Hybrid power systems Contracts Concurrent computing Costs Processor scheduling

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A cost-optimal parallel algorithm for the parentheses matching problem on an EREW PRAM

A cost-optimal parallel algorithm for the parentheses matchi...

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International Symposium on parallel Processing

作者： C.C.-Y. Chen S.K. Das Center for Research in Parallel and Distributed Computing Department of Computer Sciences University of North Texas Denton TX USA

The article presents a cost-optimal parallel algorithm for the parentheses matching problem on the EREW PRAM model. For n parentheses, the algorithm requires O(n/p+log n) time and O(n+p log p) space, employing p proce... 详细信息

关键词： parallel algorithms Phase change random access memory Data structures distributed computing Concurrent computing Arithmetic Binary trees Partitioning algorithms Read-write memory Algorithm design and analysis

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Performance of parallel spanning tree algorithms on linear arrays of transputers and Unix systems

Performance of parallel spanning tree algorithms on linear a...

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International Symposium on parallel Processing

作者： S.K. Das Cui-Qing Yang Center for Research in Parallel and Distributed Computing Department of Computer Sciences University of North Texas Denton TX USA

This paper presents empirical performance of parallel algorithms for computing a spanning tree (SPT) and a minimum spanning tree (MST) of connected graphs on the Transputer and Unix systems, where processors are configured as a one-dimensional array. The parallel MST algorithm uses a weight matrix data structure; and three implementations of the SPT algorithm are presented with unordered edge-list, linked adjacency list and adjacency matrix as data structures. The experiments are conducted with a wide range of random graphs, generated for various edge-densities (d) for a given number (n) of vertices. The edge-density is varied between 0.1 and 0.9, and the maximum number of vertices (or edges) considered are 300 (or 40000) and 500 (or 110000) for transputer and Unix systems, respectively. A maximum speed-up of 2.98 is achieved on the transputer network of eight processors, and that for the Unix system is 3.0 with four processors.< >

关键词： Tree graphs Concurrent computing distributed computing parallel algorithms Tree data structures Data structures Random number generation Communication networks Clocks Very large scale integration

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SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation

SPITFIRE: scalable parallel algorithms for test set partitio...

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VLSI Test Symposium

作者： D. Krishnaswamy E.M. Rudnick J.H. Patel P. Banerjee Center for Reliable and High Performance Computing University of Illinois Urbana-Champaign IL USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

We propose three synchronous parallel algorithms for scalable parallel test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors, The test set partitioning inherent in the algorithms overcomes the good circuit logic simulation bottleneck that exists in traditional fault partitioned approaches to parallel fault simulation. The implementations were done on a shared memory multiprocessor and on a network of workstations. Two of the algorithms show a small degree of pessimism in a few cases, with respect to the fault coverage as compared with a uniprocessor run, while the third algorithm provides the same results as in a uniprocessor run. All algorithms provide excellent speedups and perform much better than a traditional fault partitioned approach, on both shared and distributed memory parallel platforms.

关键词： parallel algorithms Circuit testing Circuit faults Partitioning algorithms Circuit simulation Logic testing Sequential analysis Very large scale integration Sequential circuits Workstations

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ON RELIABILITY ANALYSIS OF CHORDAL RINGS

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Journal of Circuits, Systems and Computers 1995年第2期5卷 199-213页

作者： AMIYA NAYAK NICOLA SANTORO Center for Parallel & Distributed Computing School of Computer Science Carleton University Ottawa Canada K1S 5B6 Canada

A common technique to improve the reliability of loop (or ring) networks is by introducing link redundancy; that is, by providing several alternative paths for communication between pairs of nodes. With alternate paths between nodes, the network can now sustain several node and link failures by bypassing the faulty components. However, faults occurring at strategic locations in a ring can prevent the computation by disrupting I/O operations, blocking the flow of information, or even segmenting the structure into pieces which can no longer be suitable for any practical purpose. An extensive characterization of fault-tolerance in ring topologies is given in this paper. This characterization augments the results known in the literature to date. The characterization has revealed several properties which describe the problem of constructing subrings and linear arrays in the presence of node failures in the original ring for a specified link configuration. Also in this paper, bounds are established on the degree of fault tolerance achievable in a redundant loop network, with a given degree of redundancy, when performing a computation that requires a minimal number of operational nodes. Also the bounds on the size of the problems guaranteed to be solved in the presence of a given number of faults in the network are derived.

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An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs

An automated and power-aware framework for utilization of IP...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： A. Jones P. Banerjee Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Technological Institute Northwestern University Evanston IL USA

Use of hand optimized Intellectual Property (IP) logic cores is prolific in hardware design. These IP cores range from rather complicated signal processing transforms and filters to arithmetic operators. While IP cores remain a standard way to utilize the improvement in FPGA technology and contend with time to market pressure through reuse, popularity of tools generating hardware descriptions from high-level languages is increasing in popularity. The PACT HDL behavioral synthesis tool attempts to combine these two methods within a power-aware framework. PACT HDL generates RTL HDL codes in VHDL and Verilog using a finite state machine (FSM) style. These codes use intrinsic operators to represent calculations such as addition, subtraction, and multiplication. The output HDL codes are passed to commercial RTL synthesis tools that generate the gate-level hardware descriptions. Each intrinsic operator is replaced with a hardware implementation of the calculation by the synthesis tool. Unfortunately, by leaving this decision to the synthesis tool, the gate-level instantiation may not be appropriate for the desired constraints, particularly those relating to power consumed. The synthesis tools tend to use combinational implementations that are area and power hungry. In some cases, the tool may not be able to instantiate the appropriate logic, such as the division operator, at all.

关键词： Power generation Field programmable gate arrays Hardware design languages Design optimization Intellectual property Logic design Signal processing Filters Arithmetic Time to market

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Resynthesis of sequential circuits for low power

Resynthesis of sequential circuits for low power

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： S. Roy P. Banerjee Ambit Design Systems Inc. Santa Clara USA Center for Parallel & Distributed Computing Northwestern University USA

At the logic level, a popular approach is to power down the sequential machine during the self-loops of the underlying finite state machine (FSM). In this work, we extend this idea to resynthesize existing sequential circuits to reduce power. We report a novel technique based on symbolic simulation of a sequential circuit to extract its self-loops without extracting the corresponding state transition diagram (STG). Since self loops may not be inherently present in the corresponding FSM, we partition the circuit heuristically and identify partial-self-loops for each partition to bring down the corresponding sub-circuit by gating the clock sub-tree feeding that partition. By using this approach, we could save up to 45% of the total power on a controller circuit of a microprocessor design, where traditional techniques could not save any power.

关键词： Sequential circuits Binary decision diagrams Circuit simulation Data structures Boolean functions Input variables Equations

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A NOTE ON THE LOAD BALANCING PROBLEM FOR COARSE-GRAINED HYPERCUBE DICTIONARY MACHINES

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JOINT INTERNATIONAL CONF ON VECTOR AND parallel PROCESSING ( CONPAR 90 - VAPP IV )

作者： DEHNE, F GASTALDO, M Center for Parallel and Distributed Computing School of Computer Science Carleton University Ottawa K1S 5B6 Canada Laboratoire de I'lnformatique du Parallelisms - IMAG Ecole Normale Superieure de Lyon Lyon cedex 07 69364 France

ISBN: (纸本)3540530657

The main problem for the design of dictionary machines on coarse grained hypercube multiprocessors, in comparison to the widely studied dictionary problem for fine grained hypercube multiprocessors, is that due to unequal distribution of the inserted and deleted records, the sizes of the sets stored at the individual processors may vary considerably. This problem, which is usually referred to as the load balancing problem, may lead to considerable degradation of the dictionary machine's performance. In this note we show that the load balancing problem for coarse grained hypercube dictionary machines can be solved with provable bounds on the sizes of the data sets, and with only little computational overhead. © Springer-Verlag Berlin Heidelberg 1990.

关键词： Geometry

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Noncontiguous I/O accesses through MPI-IO 03

Noncontiguous I/O accesses through MPI-IO

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IEEE/ACM International Symposium on Cluster computing and the Grid (CCGRID)

作者： A. Ching A. Choudhary K. Coloma Wei-keng Liao R. Ross W. Gropp Center for Parallel and Distributed Computing Northwestern University Evanston IL USA Argonne National Laboratory Argonne IL USA

ISBN: (纸本)9780769519197

I/O performance remains a weakness of parallel computing systems today. While this weakness is partly attributed to rapid advances in other system components, I/O interfaces available to programmers and the I/O methods supported by file systems have traditionally not matched efficiently with the types of I/O operations that scientific applications perform, particularly noncontiguous accesses. The MPI-IO interface allows for rich descriptions of the I/O patterns desired for scientific applications and implementations such as ROMIO have taken advantage of this ability while remaining limited by underlying file system methods. A method of noncontiguous data access, list I/O, was recently implemented in the parallel Virtual File System (PVFS). We implement support for this interface in the ROMIO MPI-IO implementation. Through a suite of noncontiguous I/O tests we compared ROMIO list I/O to current methods of ROMIO noncontiguous access and found that the list I/O interface provides performance benefits in many noncontiguous cases.

关键词： File systems Testing distributed computing Mathematics Computer science Laboratories parallel processing Programming profession Tiles Checkpointing

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parallel branch and bound on fine-grained hypercube multiprocessors

Parallel branch and bound on fine-grained hypercube multipro...

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International Conference on Tools for Artificial Intelligence (ICTAI)

作者： F. Dehne A.G. Ferreira A. Rau-Chaplin Center for Parallel and Distributed Computing School of Computer Science Carleton University Ottawa Canada Laboratoire de I'lnformatique du Parallelisme-IMAG Ecole Normale Superieure Lyon France Center for Parallel and Distributed Computing. School of Computer Science Carleton University Ottawa Canada

An efficient branch and bound algorithm for fine-grained hypercube multiprocessors is presented. The method uses a global storage allocation scheme where all processors collectively store all back-up paths such that each processor needs to store only a constant amount of information. At each iteration of the algorithm, all nodes of the current back-up tree may decide whether they need to create new children, be pruned, or remain unchanged. An algorithm that, on the basis of these decisions, updates the current back-up tree and distributes global information in O(log m) steps, where m is the current number of nodes, is described. This method also provides a dynamic allocation mechanism that obtains optimal load balancing. Another important property of the method is that, even if very drastic changes in the current back-up tree occur, the performance of the load balancing mechanism remains constant. The method is currently being implemented on the Connection Machine.< >

关键词： Hypercubes Load management distributed computing Computer science Search methods Linear programming Artificial intelligence Operations research High definition video Concurrent computing

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