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A parallel algorithm for timing-driven global routing for standard cells

A parallel algorithm for timing-driven global routing for st...

引用

International Conference on parallel Processing (ICPP)

作者： Zhaoyun Xing P. Banerjee Sun MicroSystems Laboratories Inc. Palo Alto CA USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

The timing-driven global routing problem is an extremely important and time consuming phase of any automated layout system. In this paper, by integrating high performance interconnection tree construction, wire-sizing, and switch-able segment channel optimization together, we propose an adaptive timing-driven global routing algorithm which minimizes the timing delay as well as circuit area. Our experiments on MCNC benchmarks show that our timing-driven global routing algorithm reduces the maximum path delays significantly from the global router TimberWolfSC. Based on this adaptive timing-driven global routing algorithm, a parallel algorithm on timing-driven global routing for standard cells is given. This algorithm has been implemented on an 8 processor IBM J-40 shared memory multi-processor by using the Message Passing Interface (MPI). Our experimental results show good speedup and circuit delay results for this parallel algorithm using MCNC benchmark circuits.

关键词： parallel algorithms Delay Routing Integrated circuit interconnections Switching circuits Timing Message passing Circuit topology Contracts Algorithm design and analysis

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On design of cluster and grid computing environment toolkit for bioinformatics applications∗ 6th

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6th International Workshop on distributed computing, IWDC 2004

作者： Yang, Chao-Tung Kuo, Yu-Lun Li, Kuan-Ching Gaudiot, Jean-Luc High Performance Computing Laboratory Dept. of Computer Science and Information Engineering Tunghai University Taichung40744 Taiwan Parallel and Distributed Processing Center Dept. of Computer Science and Information Management Providence University Taichung43301 Taiwan Parallel and Scalable Computer Architecture Laboratory Dept. of Electrical Engineering and Computer Science University of California – Irvine IrvineCA92697 United States

ISBN: (纸本)9783540240761

In this paper, we present BioGrid, a novel computing resource that combines advantages of grid computing technology with bioinformatics parallel applications. The grid environment permits the sharing of a large amount of idle computing resources and data. The investigation of bioinformatics demands orders of magnitude of computing resources and in parallel, the biological data are growing in such a high speed. By using BioGrid, we plan to integrate and share resources and biological data using the grid computing technology. Still in this paper, the well-known FASTA application is performed as matter of testing and analysis in our grid computing platform, as goal to show the improved efficiency and reduced computation time. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Bioinformatics

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Noncontiguous I/O through PVFS

Noncontiguous I/O through PVFS

引用

IEEE International Conference on Cluster computing

作者： Avery Ching A. Choudhary Wei-keng Liao R. Ross W. Gropp Center for Parallel and Distributed Computing Northwestern University Evanston IL USA Mathematics and Computer Science Division Argonne National Laboratory Argonne IL USA

With the tremendous advances in processor and memory technology, I/O has risen to become the bottleneck in high-performance computing for many applications. The development of parallel file systems has helped to ease the performance gap, but I/O still remains an area needing significant performance improvement. Research has found that noncontiguous I/O access patterns in scientific applications combined with current file system methods, to perform these accesses lead to unacceptable performance for large data sets. To enhance performance of noncontiguous I/O, we have created list I/O, a native version of noncontiguous I/O. We have used the parallel Virtual File System (PVFS) to implement our ideas. Our research and experimentation shows that list I/O outperforms current noncontiguous I/O access methods in most I/O situations and can substantially enhance the performance of real-world scientific applications.

关键词： File systems File servers Concurrent computing Linux distributed computing Application software Costs Network servers Mathematics Computer science

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A dynamic load balancing strategy for channel assignment using selective borrowing in cellular mobile environment 96

A dynamic load balancing strategy for channel assignment usi...

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Proceedings of the 2nd annual international conference on Mobile computing and networking

作者： Sajal K. Das Sanjoy K. Sen Rajeev Jayaram Center for Research in Parallel and Distributed Computing Department of Computer Sciences University of North Texas P.O. Box 13886 Denton TX

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Efficient construction of catastrophic patterns for VLSI reconfigurable arrays with bidirectional links

Efficient construction of catastrophic patterns for VLSI rec...

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International Conference on computing and Information (ICCI)

作者： A. Nayak L. Pagli N. Santoro Center for Parallel & Distributed Computing School of Computer Science Carleton University Ottawa Canada Dipartimento di Scienze dellInformazione University of Pisa Pisa Italy

Patterns of faults that are catastrophic for regular architectures, particularly the systolic arrays, have been studied. For a given link configuration, there are many fault patterns which are catastrophic. Among those, there is a particular fault pattern, called the reference fault pattern, which is crucial for the development of testing techniques; furthermore, the efficiency of any testing algorithm can be further improved in the presence of efficient algorithms for constructing the reference fault pattern. The authors develop a new algorithm for the construction of the reference fault pattern for VLSI reconfigurable arrays in which the links are bidirectional. The complexity of the new algorithm is O(kN) which is a significant improvement over the existing O(N/sup 2/) algorithm, where k is the number of bypass links, and N is the length of the largest bypass link.< >

关键词： Very large scale integration Redundancy Systolic arrays distributed computing Computer science Fault tolerance Clustering algorithms System testing Fault diagnosis Sufficient conditions

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Recognition of catastrophic faults

Recognition of catastrophic faults

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

For a given design, it is not difficult to identify a set of elements whose failure will have catastrophic consequence. There exist many patterns (random distribution) of faults, not in a block, which can be fatal for the system. Therefore, the characterization of such fault patterns is crucial for the identification, testing and detection of such catastrophic events. This paper, is concerned with the development of efficient recognition schemes; that is, efficient mechanisms which automatically determine whether or not an observed/detected pattern of faults will have catastrophic consequences. The problem of recognizing whether a fault pattern is catastrophic has been addressed.< >

关键词： Redundancy Pattern recognition Fault tolerance Fault detection Event detection Testing distributed computing Computer science Fault diagnosis Sufficient conditions

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parallel algorithms for force directed scheduling of flattened and hierarchical signal flow graphs

Parallel algorithms for force directed scheduling of flatten...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： P. Prabhakaran P. Banerjee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

In this paper we present some novel algorithms for scheduling hierarchical signal flow graphs in the domain of high-level synthesis. There are several key contributions of this paper. First, we develop a novel extension of the force directed scheduling problem which naturally handles loops and conditionals by coming up with a scheme of scheduling hierarchical signal flow graphs. Second, we develop three new parallel algorithms for the scheduling problem. Third, our parallel algorithms are portable across a wide range of parallel platforms. We report results on a set of high-level synthesis benchmarks on 8-processor SGI Challenge and a network of 4 SUN SPARCstation5 work stations. Finally, while some parallel algorithms for VLSI CAD reported by earlier researchers have reported a loss of qualities of results, our parallel algorithms produce exactly the same results as the sequential algorithms on which they are based.

关键词： parallel algorithms Flow graphs Processor scheduling Concurrent computing Scheduling algorithm Contracts Cost function Broadcasting

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A recursive-adjustment co-allocation scheme in data grid environments 1

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6th International Conference on Algorithms and Architectures for parallel Processing, ICA3PP

作者： Yang, Chao-Tung Yang, I.-Hsien Li, Kuan-Ching Hsu, Ching-Hsien High Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung 40704 Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung 43301 Taiwan Department of Computer Science and Information Engineering Chung Hua University Hsinchu 300 Taiwan

ISBN: (数字)9783540320715

ISBN: (纸本)3540292357

The co-allocation architecture was developed in order to enable parallel downloads of datasets from multiple servers. Several co-allocation strategies have been coupled and used to exploit rate differences among various client-server links and to address dynamic rate fluctuations by dividing files into multiple blocks of equal sizes. However, a major obstacle, the idle time of faster servers having to wait for the slowest server to deliver the final block, makes it important to reduce differences in finish time among replica servers. In this paper, we propose a dynamic co-allocation scheme, namely Recursive-Adjustment Co-Allocation scheme, to improve the performance of data transfer in Data Grids. Our approach reduces the idle time spent waiting for the slowest server and decreases data transfer completion time. © Springer-Verlag Berlin Heidelberg 2005.

关键词： parallel processing systems

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On utilization of the grid computing technology for video conversion and 3D rendering

On utilization of the grid computing technology for video co...

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3rd International Symposium on parallel and distributed Processing and Applications, ISPA 2005

作者： Yang, Chao-Tung Lai, Chuan-Lin Li, Kuan-Ching Hsu, Ching-Hsien Chu, William C. High Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung 40704 Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung 43301 Taiwan Department of Computer Science and Information Engineering Chung Hua University Hsinchu 300 Taiwan

ISBN: (纸本)3540297693

In this paper, we investigate the recent popular computing technique called Grid computing, and use video conversion and 3D rendering applications to demonstrate this technology's effectiveness and high performance. We also report on developing a resource broker called Phantom that runs on our grid computing testbed and whose main function is querying nodes in grid computing environments and showing their system information to aid in selecting the best nodes for job assignments to have the jobs executed in the least amount of time. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Computability and decidability

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parallel algorithms for simultaneous scheduling, binding and floorplanning in high-level synthesis

Parallel algorithms for simultaneous scheduling, binding and...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： P. Prabhakaran P. Banerjee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign IL USA Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

With small device features in submicron technologies, interconnection delays play a dominant part in cycle time. Hence, it is important to consider the impact of physical design during high level synthesis. In comparison to a traditional approach which separates high-level synthesis from physical design, an algorithm which is able to make these stages interact very closely, would result in solutions with lower latency and area. However, such an approach could result in increased runtimes. parallel processing is an attractive way of reducing the runtimes. In this paper, two parallel algorithms for simultaneous scheduling, binding and floorplanning algorithm are presented. A detailed hardware model is considered, taking into account multiplexor and register areas and delays. Experimental results are reported on an IBM SP-2 multicomputer, with close to linear speedups for a set of benchmark circuits.

关键词： parallel algorithms High level synthesis Runtime Integrated circuit interconnections Delay effects Algorithm design and analysis parallel processing Scheduling algorithm Hardware Registers

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