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5th International parallel Processing Symposium, IPPS 1991

作者： Chen, Calvin C.-Y. Das, Sajal K. Center for Research in Parallel and Distributed Computing Department of Computer Sciences University of North Texas DentonTX76203-3886 United States

We present a cost-optimal parallel algorithm for the parentheses matching problem on the EREW PRAM model For n parentheses, the algorithm requires O(n/p + log n) time and O(n + p log p) space, employing p processors. ... 详细信息

ISBN: (纸本)0818691670

关键词： Computational complexity

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Untrusted Hardware Causes Double-Fetch Problems in the I/O Memory

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Journal of Computer Science & Technology 2018年第3期33卷 587-602页

作者： Kai Lu Peng-Fei Wang Gen Li Xu Zhou College of Computer National University of Defense Technology Changsha 410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China Collaborative Innovation Center of High-Performance Computing National University of Defense Technology Changsha 410073 China

The double fetch problem occurs when the data is maliciously changed between two kernel reads of the supposedly same data, which can cause serious security problems in the kernel. Previous research focused on the double fetches between the kernel and user applications. In this paper, we present the first dedicated study of the double fetch problem between the kernel and peripheral devices （aka. the hardware double fetch）. Operating systems communicate with peripheral devices by reading from and writing to the device mapped I/O （input and output） memory. Owing to the lack of effective validation of the attached hardware, compromised hardware could flip the data between two reads of the same I/O memory address, causing a double fetch problem. We propose a static pattern-matching approach to identify the hardware double fetches from the Linux kernel. Our approach can analyze the entire kernel without relying on the corresponding hardware. The results are categorized and each category is analyzed using case studies to discuss the possibility of causing bugs. We also find four previously unknown double-fetch vulnerabilities, which have been confirmed and fixed after reporting them to the maintainers.

关键词： hardware double fetch double-fetch bug I/O memory peripheral device double-fetch vulnerability

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DFTracker: detecting double-fetch bugs by multi-taint parallel tracking

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Frontiers of Computer Science 2019年第2期13卷 247-263页

作者： Pengfei WANG Kai LU Gen LI Xu ZHOU Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China Collaborative Innovation Center of High Performance Computing National University of Defense Technology Changsha 410073 China

A race condition is a common trigger for concurrency bugs. As a special case, a race condition can also occur across the kernel and user space causing a doublefetch bug, which is a field that has received little research attention. In our work, we first analyzed real-world doublefetch bug cases and extracted two specific patterns for doublefetch bugs. Based on these patter ns, we proposed an approach of multi-taint parallel tracking to detect double-fetch bugs. We also implemented a prototype called DFTracker (doublefetch bug tracker), and we evaluated it with our test suite. Our experiments demonstrated that it could effectively find all the double-fetch bugs in the test suite including eight realworld cases with no false negatives and minor false positives. In addition, we tested it on Linux kernel and found a new double-fetch bug. The execution overhead is approximately 2x for single-file cases and approximately 9x for the whole kernel test, which is acceptable. To the best of the authors1 knowledge, this work is the first to introduce multi-taint parallel tracking to double-fetch bug detection—an innovative method that is specific to double-fetch bug features—and has better path coverage as well as lower runtime overhead than the widely used dynamic approaches.

关键词： multi-taint parallel tracking double fetch race condition between kernel and user time of check to time of use real-world case analysis Clang Static Analyzer

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A dynamic load balancing algorithm for conservative parallel simulations

A dynamic load balancing algorithm for conservative parallel...

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International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： A. Boukerche S.K. Das Center for Research in Parallel and Distributed Computing Center for Research in Parallel and Distributed Computing University of North Texas Denton TX USA

Load balancing is an important component in improving the efficiency of distributed systems because it distributes an even workload over all the processors. This paper considers the problem of load-balancing a conservative parallel simulation for execution on a multicomputer. The synchronization protocol makes use of Chandy-Misra (1979) null-messages. An earlier study conducted by Boukerche and Tropper (1994) showed that static load balancing for conservative parallel simulation is effective when the workload can be sufficiently well characterized beforehand. In this paper, we present a dynamic load balancing algorithm which assumes no compile-time knowledge about the workload parameters. It is based upon a process migration mechanism and the notion of CPU-queue length, which indicates the workload at each processor. We discuss the algorithm and its implementation, and report on the performance results of a simulation of FCFS (first-come, first-served) queueing network models on an Intel Paragon A4.

关键词： Load management Heuristic algorithms Computational modeling distributed computing Concurrent computing Protocols Performance gain Partitioning algorithms Computer simulation Constraint optimization

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Leveraging the Compute Power of Two HPC Systems for Higher-Dimensional Grid-Based Simulations with the Widely-distributed Sparse Grid Combination Technique 23

Leveraging the Compute Power of Two HPC Systems for Higher-D...

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2023 International Conference for High Performance computing, Networking, Storage and Analysis, SC 2023

作者： Pollinger, Theresa Van Craen, Alexander Niethammer, Christoph Breyer, Marcel Pflüger, Dirk Institute for Parallel and Distributed Systems Universität Stuttgart Stuttgart Germany High Performance Computing Center Universität Stuttgart Stuttgart Germany

ISBN: (纸本)9798400701092

Grid-based simulations of hot fusion plasmas are often severely limited by computational and memory resources;the grids live in four- to six-dimensional space and thus suffer the curse of dimensionality. However, high resolutions are required to fully capture the physics of interest. The sparse grid combination technique is a multi-scale method in which many anisotropically coarse resolved grids are used to approximate a fine-scale solution - -and it alleviates the curse of *** paper presents the core concepts of the widely-distributed combination technique, which allows us to use the compute power and memory of more than one HPC system for the same simulation. We apply the sparse grid combination technique to a six-dimensional advection problem serving as a proxy for plasma simulations. The full-grid solution approximated by the combination technique would contain ≈ 5 ZB if computed with conventional grid-based methods. Even the combination technique simulation operates on ≈ 1 × 1011 double-precision degrees of freedom, or 988 GB, plus the supporting sparse grid data structures. We propose a new approach to divide the compute load between the two HPC systems, requiring only 76 GB to be exchanged. Based on this, we have realized the first synchronous combination technique simulation using two HPC systems, in our case the two German Tier-0 supercomputers HAWK and SuperMUC-NG. On two systems, the simulation can be computed at an average overhead of ≈ 35 % (108 s per combination step) for file I/O and transfer. The presented concepts apply to any pair of HPC systems if high-speed data transfer is possible. © 2023 ACM.

关键词： Supercomputers

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PDRL-CM: An efficient cooperative caching management method for vehicular networks based on deep reinforcement learning

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Ad Hoc Networks 2025年 176卷

作者： Ou, Pingjie Chen, Ningjiang Yang, Long School of Computer and Electronic Information Guangxi University Nanning Guangxi530004 China Key Laboratory of Parallel Distributed and Intelligent Computing Education Department of Guangxi Zhuang Autonomous Region Nanning Guangxi530004 China The Guangxi Intelligent Digital Services Research Center of Engineering Technology Nanning Guangxi530004 China

In vehicular networks, onboard devices face the challenge of limited storage, and computational resources constrain their processing and storage capabilities. This limitation is particularly significant for applications that require complex computations and real-time responses. Additionally, limited storage capacity reduces the range of cacheable data, which can impact the immediate availability of data and the continuity of services. Therefore, improving cache utilization and meeting vehicles’ real-time data demands pose significant challenges. Deep reinforcement learning can optimize the issues arising from agents’ continuously changing state and action spaces due to increasing request demands. However, training the network may encounter instability and convergence difficulties in dynamic and complex environments or situations with sparse rewards. In response to these issues, this paper proposes a Priority-based Deep Reinforcement Learning Collaborative Cache Management method (PDRL-CM). PDRL-CM first designs a lightweight cache admission strategy that leverages data's inherent and combined attributes. It then makes cache admission decisions Using Monte Carlo sampling and a max-value search strategy combined with a feedforward neural network. Secondly, the method considers minimizing system latency and reducing vehicle energy consumption as joint optimization problems. An improved deep reinforcement learning algorithm solves this problem and makes cache-sharding decisions. A prioritized experience replay mechanism is incorporated to adjust the network prediction model quickly and accelerate the convergence process. Experimental results indicate that, compared to existing DRL-based caching methods, PDRL-CM offers faster data processing efficiency and higher cache hit rates under varying vehicle density, storage capacity, and content volume conditions. © 2025

关键词： Cache memory

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A mobile agent prototype for distributed search 3

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3rd International Workshop on Mobile Agents for Telecommunication Applications, MATA 2001

作者： Velazquez, Elio Santoro, Nicola Nayak, Amiya Center for Parallel and Distributed Computing School of Computer Science Carleton University OttawaONK1S 5B6 Canada

ISBN: (纸本)3540424601

In this paper, we propose a mobile agent platform as an alternative to a message passing approach to solve a distributed search problem. The search problem is analyzed from two different perspectives, the single travelling agent case and the multiple travelling agents case. We conduct several experiments to measure the performance of the mobile agent solutions as well as the stationary agents for different network topologies and observe that the multiple agents approach performs better when the number of nodes in the network increases. The tree topology, in particular, gives the best overall performance among all topologies considered. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Mobile agents

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Bounds on performance of VLSI processor arrays 5

Bounds on performance of VLSI processor arrays

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5th International parallel Processing Symposium, IPPS 1991

作者： Nayak, Amiya Santoro, Nicola Center for Parallel and Distributed Computing School of Computer Science Carleton University OttawaK1S 5B6 Canada

ISBN: (纸本)0818691670

This paper discusses the effect of processor failures on computation performed on two-dimensional VLSI processor arrays. Previously established properties of catastrophic fault patterns are used to study inherent limits to reconfigurability of these regular architectures. Bounds on number of faults the system can tolerate to provide guaranteed performance are derived. These results are the generalization of the results obtained in the case of one-dimensional processor arrays. © 1991 IEEE.

关键词： VLSI circuits

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Implementing data structures on a hypercube multiprocessor, and applications in parallel computational geometry 15th

Implementing data structures on a hypercube multiprocessor, ...

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15th International Workshop on Graph-Theoretic Concepts in Computer Science, WG 1989

作者： Dehne, Frank Rau-Chaplin, Andrew Center for Parallel and Distributed Computing School of Computer Science Carleton University OttawaK1S 5B6 Canada

ISBN: (纸本)9783540522928

In this paper, we study the problem of implementing standard data structures on a hypercube multiprocessor. We present a technique for efficiently executing multiple independant search processes on a class of graphs called ordered h-level graphs. We show how this technique can be utilized to implement a segment tree on a hypercube, thereby obtaining O(log2n) time algorithms for solving the next element search problem, the trapezoidal decomposition problem, the triangulation problem, and the (multiple) planar point location problem. © Springer-Verlag Berlin Heidelberg 1990.

关键词： Computational geometry

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Exploiting web document structure to improve storage management in proxy caches 1

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9th International Conference on High Performance computing, HiPC 2002

作者： Abhari, Abdolreza Dandamudi, Sivarama P. Majumdar, Shikharesh Center for Parallel and Distributed Computing School of Computer Science Carleton University Ottawa Canada Deptartment of Systems and Computer Engineering Carleton University Ottawa Canada

ISBN: (数字)9783540362654

ISBN: (纸本)3540003037

Proxy caches are essential to improve the performance of World Wide Web and to enhance user perceived latency. In this paper, we propose a new Web object based policy to manage the storage system of a proxy cache. We propose two techniques to improve the storage system performance. The first technique is concerned with prefetching the related files belonging to a Web object, from the disk to main memory. This prefetching improves performance as most of the files can be provided from the main memory instead of proxy disk. The second technique stores the Web object members in contiguous disk blocks in order to reduce the disk access time. This in turn reduces the disk response time. We have used trace-driven simulations to study the performance improvements one can obtain with these two techniques. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Proxy caches

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