This paper presents empirical performance of parallel algorithms for computing a spanning tree (SPT) and a minimum spanning tree (MST) of connected graphs on the Transputer and Unix systems, where processors are confi...
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We present a cost-optimal parallel algorithm for the parentheses matching problem on the EREW PRAM model For n parentheses, the algorithm requires O(n/p + log n) time and O(n + p log p) space, employing p processors. ...
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The parentheses matching problem is to determine the mate of each parenthesis in a balanced string of n parentheses. In this paper, we present three novel and elegant parallel algorithms for this problem on parallel r...
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The authors present cost-optimal parallel algorithms for depth-order (e.g., pre-, in-, and post-order) and level-order (e.g., breadth-first and breadth-depth) traversals of general trees with n nodes. Each of the algo...
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The authors present cost-optimal parallel algorithms for depth-order (e.g., pre-, in-, and post-order) and level-order (e.g., breadth-first and breadth-depth) traversals of general trees with n nodes. Each of the algorithms requires O(n/p+log n) time using p >
The article presents a cost-optimal parallel algorithm for the parentheses matching problem on the EREW PRAM model. For n parentheses, the algorithm requires O(n/p+log n) time and O(n+p log p) space, employing p proce...
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The article presents a cost-optimal parallel algorithm for the parentheses matching problem on the EREW PRAM model. For n parentheses, the algorithm requires O(n/p+log n) time and O(n+p log p) space, employing p processors. Thus, for p >
This paper presents empirical performance of parallel algorithms for computing a spanning tree (SPT) and a minimum spanning tree (MST) of connected graphs on the Transputer and Unix systems, where processors are confi...
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This paper presents empirical performance of parallel algorithms for computing a spanning tree (SPT) and a minimum spanning tree (MST) of connected graphs on the Transputer and Unix systems, where processors are configured as a one-dimensional array. The parallel MST algorithm uses a weight matrix data structure; and three implementations of the SPT algorithm are presented with unordered edge-list, linked adjacency list and adjacency matrix as data structures. The experiments are conducted with a wide range of random graphs, generated for various edge-densities (d) for a given number (n) of vertices. The edge-density is varied between 0.1 and 0.9, and the maximum number of vertices (or edges) considered are 300 (or 40000) and 500 (or 110000) for transputer and Unix systems, respectively. A maximum speed-up of 2.98 is achieved on the transputer network of eight processors, and that for the Unix system is 3.0 with four processors.< >
Identification, characterization, and construction of fault patterns that are catastrophic for linear systolic arrays are discussed. It is shown that for a given link configuration in the array, it is possible to iden...
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Identification, characterization, and construction of fault patterns that are catastrophic for linear systolic arrays are discussed. It is shown that for a given link configuration in the array, it is possible to identify all PE (processing element) catastrophic fault patterns. The requirement on the minimum number of faults in a fault pattern and its spectrum (spread out) for it to be catastrophic is shown to be a function of the length of the longest bypass link available, and not of the total number of bypass links. The paper also gives bounds on the width of a catastrophic fault spectrum.< >
Microservice architectures are increasingly used to modularize IoT applications and deploy them in distributed and heterogeneous edge computing environments. Over time, these microservice-based IoT applications are su...
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Microservice architectures are increasingly used to modularize IoT applications and deploy them in distributed and heterogeneous edge computing environments. Over time, these microservice-based IoT applications are susceptible to performance anomalies caused by resource hogging (e.g., CPU or memory), resource contention, etc., which can negatively impact their Quality of Service and violate their Service Level Agreements. Existing research on performance anomaly detection for edge computing environments focuses on model training approaches that either achieve high accuracy at the expense of a time-consuming and resource-intensive training process or prioritize training efficiency at the cost of lower accuracy. To address this gap, while considering the resource constraints and the large number of devices in modern edge platforms, we propose two clustering-based model training approaches: (1) intra-cluster parameter transfer learning-based model training (ICPTL) and (2) cluster-level model training (CM). These approaches aim to find a trade-off between the training efficiency of anomaly detection models and their accuracy. We compared the models trained under ICPTL and CM to models trained for specific devices (most accurate, least efficient) and a single general model trained for all devices (least accurate, most efficient). Our findings show that ICPTL’s model accuracy is comparable to that of the model per device approach while requiring only 40% of the training time. In addition, CM further improves training efficiency by requiring 23% less training time and reducing the number of trained models by approximately 66% compared to ICPTL, yet achieving a higher accuracy than a single general model.
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