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CONF ON supercomputing ( supercomputing 89 )

作者： EMRATH, PA GHOSH, S PADUA, DA Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 305 Talbot Laboratory 104 South Wright Street Urbana Illinois

ISBN: (纸本)0897913418

One of the major difficulties of explicit parallel programming for a shared memory machine model is detecting the potential for nondeterminacy and identifying its causes. There will often be shared variables in a parallel program, and the tasks comprising the program may need to be synchronized when accessing these *** paper discusses this problem and presents a method for automatically detecting non-determinacy in parallel programs that utilize event style synchronization instructions, using the Post, Wait, and Clear primitives. With event style synchronization, especially when there are many references to the same event, the difficulty lies in computing the execution order that is guaranteed given the synchronization instructions and the sequential components of the program. The main result in this paper is an algorithm that computes such an execution order and yields a Task Graph upon which a nondeterminacy detection algorithm can be *** have focused on events because they are a frequently used synchronization mechanism in parallel versions of Fortran, including Cray [Cray87], IBM [IBM88], Cedar [GPHL88], and PCF Fortran [PCF88].

关键词： Computer programming

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Computer architecture education at the University of Illinois: Current status and some thoughts 2

Computer architecture education at the University of Illinoi...

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2nd Annual Workshop on Computer Architecture Education, WCAE 1996

作者： Torrellas, Josep Center for Supercomputing Research and Development Computer Science Department University of Illinois Urbana-ChampaignIL61801 United States

ISBN: (纸本)9781450347389

The University of Illinois has traditionally been a major center for computer architecture education and research in the nation. This short paper briefly describes the computer architecture curriculum at the University of Illinois and discusses a few ideas for improving the computer architecture education of our students. In particular, to improve the education of undergraduates, we suggest a higher emphasis on parallel architectures and programming, and the provision of practical experiences. For graduate students, we argue about the need to develop close links with industry and educate graduate students from other scientific and engineering disciplines. © 1996, Association for Computing Machinery, Inc. All rights reserved.

关键词： Parallel architectures

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Collective Movement Simulation:Methods and Applications

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Machine Intelligence research 2024年第3期21卷 452-480页

作者： Hua Wang Xing-Yu Guo Hao Tao Ming-Liang Xu School of Computer and Artificial Intelligence Zhengzhou UniversityZhengzhou450001China Engineering Research Center of Intelligent Swarm Systems Ministry of EducationZhengzhou450001China National Supercomputing Center in Zhengzhou Zhengzhou450001China China Ship Development and Design Center Wuhan430060China

Collective movement simulations are challenging and important in many areas,including life science,mathematics,physics,information science and public *** this survey,we provide a comprehensive review of the state-of-the-art techniques for collective movement *** start with a discussion on certain concepts to help beginners understand it more ***,we analyze the intelligence among different collective objects and the emphasis in different ***,we classify existing collective movement simulation methods into four categories according to their effects,namely versatility,accuracy,dynamic adaptability,and assessment feedback ***,we introduce five applications of layout optimization,emergency control,dispatching,unmanned systems,and other derivative ***,we summarize possible future research directions.

关键词： Collective movement simulation multiple objects multiple discipline simulation effect collective intelligence

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A high performance software defined radio system architecture and development environment for a wide range of applications

A high performance software defined radio system architectur...

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2018 International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2018

作者： Hussain, Tassadaq Khan, Musawir Rehman, Mujeeb Ur Akram, Wasim Anayat, Khalid Arshad, Ahtisham Akbar, Ahsan Habib, Asad Riphah International University Islamabad Pakistan Barcelona Supercomputing Center Spain Unal Color of Education Research and Development Pakistan

ISBN: (纸本)9781538613702

Software Defined Radio (SDR) is a radio communication technique which converts hardware problems to software problems using a programmable processing system. With the increase of SDR applications, the demand for high bandwidth and signal processing also increased. Therefore, the SDR system needs a programmable and scalable multicore processing hardware architecture. In this work, we proposed a scalable multi-core, programmable and parameterizable High Performance Software Defined Radio system architecture and software development environment. The proposed system uses heterogeneous processing cores including CPU, SIMD, and FPGA architectures and supports C++, Python, and Dataflow programming environment. To validate the effectiveness of the proposed system, we implemented and tested it on a FPGA based Altera DE1-SoC and heterogeneous multi-core development board. In order to prove that the system is efficient in a variety of scenarios, different modulation techniques are used. © 2018 IEEE.

关键词： System-on-chip

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FALCON: A MATLAB interactive restructuring compiler 8th

FALCON: A MATLAB interactive restructuring compiler

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Proceedings of the 1995 8th International Workshop on Languages and Compilers for Parallel Computing

作者： De, Rose, L. Gallivan, K. Gallopoulos, E. Marsolf, B. Padua, D. Center for Supercomputing Research Development and Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana 61801 IL United States

ISBN: (纸本)9783540607656

The development of efficient numerical programs and library routines for high-performance parallel computers is a complex task requiring not only an understanding of the algorithms to be implemented, but also detailed knowledge of the target machine and the software environment. In this paper, we describe a programming environment that can utilize such knowledge for the development of high-performance numerical programs and libraries. This environment uses an existing highlevel array language (MATLAB) as source language and performs static, dynamic, and interactive analysis to generate Fortran 90 programs with directives for parallelism. It includes capabilities for interactive and automatic transformations at both the operation-level and the functional- or algorithm-level. Preliminary experiments, comparing interpreted MATLAB programs with their compiled versions, show that compiled programs can perform up to 48 times faster on a serial machine, and up to 140 times faster on a vector machine. © Springer-Veriag Berlin Heidelberg 1996.

关键词： MATLAB

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development and Evaluation of High-Density Multi-GPU Sub-System Using PCI Express Expansion Hardware

Development and Evaluation of High-Density Multi-GPU Sub-Sys...

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2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020

作者： Kim, Young woo Oh, Myung-Hoon Park, Chan-Yeol ETRI Data Centric Computing System Research Section Korea Republic of KISTI Center for Development of Supercomputing System Korea Republic of

ISBN: (纸本)9781728161648

In this paper, we develop and evaluate a high-density multi-GPU hardware sub-system for high performance computing and deep learning. The high-density multi-GPU hardware is implemented as an out-of-box hardware by extending PCI Express system bus via multi-Gbps class cable assemblies from a server. The high-density multi-GPU hardware extends the PCI Express in a multiple-ways and provides multiple GPUs for a server. The high-density multi-GPU hardware is developed to fit into 21 inches OCP Open Rack Vl and V2 rack and chassis having density of 12 GPUs in 4OU (Open rack Unit) height. The HPL and deep learning applications are tested to evaluate the performance of the developed high-density multi-GPU hardware. The initial test result of HPL is shown that the maximum performance of 36.22 TFLOPS (efficiency of 63.4%) with 12 NVIDIA P100 on triple sever nodes. For deep learning application, the resnet50 result of 3, 187.2 images/sec is obtained with 12 NVIDIA P100 on single sever node with synthetic data. The experimental results show that the developed multi-GPU hardware sub-system exhibits relatively good scalability in a single node especially deep learning applications than the HPL. © 2020 IEEE.

关键词： Expansion

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Comparison and analysis of software and directory coherence schemes 91

Comparison and analysis of software and directory coherence ...

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Proceedings of supercomputing '91

作者： Chen, Yung-Chin Veidenbaum, Alexander V. Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 305 Talbot-104 South Wright Street Urbana Illinois

ISBN: (纸本)0818621583

Directory schemes and software schemes have been proposed to solve the cache coherence problem for the MIN-based large-scale multiprocessor system. The authors compare the performance of the two schemes using trace-driven simulation including the effect of false sharing caused by a nontrivial cache line size. It is shown that the simplest software scheme can have a hit ratio and shared memory traffic comparable to those of the directory scheme. The invalidations and the sharing behavior of the director scheme are classified and analyzed.

关键词： Computer systems, Digital

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EFFICIENT CIRCUIT PARTITIONING ALGORITHMS FOR PARALLEL LOGIC SIMULATION 89

EFFICIENT CIRCUIT PARTITIONING ALGORITHMS FOR PARALLEL LOGIC...

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CONF ON supercomputing ( supercomputing 89 )

作者： PATIL, S BANERJEE, P POLYCHRONOPOULOS, CD Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL Center for Supercomputing Research and Development Talbot Laboratory University of Illinois Urbana IL

ISBN: (纸本)0897913418

General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. This paper addresses logic simulation on parallel machines by exploiting the concurrency in the circuit being simulated (called data parallelism) as opposed to exploiting parallelism inherent in the simulation algorithm itself (called functional parallelism). The most crucial step in obtaining the maximum parallelism using data parallelism is the partitioning of circuit elements. We introduce a cost function which tries to model the simulation of a logic circuit in a parallel environment. The cost function tries to estimate the parallel run time for logic simulation given the processor assignment and the underlying multiprocessor architecture. We then present different heuristic algorithms to partition the circuit and evaluate the efficiency of these algorithms using the proposed cost function. Partitioning algorithms for both event-driven and compiled code simulation are given.

关键词： Logic circuits

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An effective synchronization network for large multiprocessor systems 5

An effective synchronization network for large multiprocesso...

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5th International Parallel Processing Symposium, IPPS 1991

作者： Hsu, William Tsun-Yuk Yew, Pen-Chung Center for Supercomputing Research and Development 305 Talbot Labs 104 S. Wright UrbanaIL61801 United States

ISBN: (纸本)0818691670

In large multiprocessor systems, fast synchronisation is crucial for high performance. However, synchronisation traffic tends to create "hot-spots" in shared memory and cause network congestion. Multistage shuffle-exchange networks hare been proposed and built to handle synchronisation traffic. Software combining schemes have also been proposed to relieve network congestion caused by hot-spots. However, multistage combining networks are very expensive and software combining is very slow. In this paper, we propose a single-stage combining network to handle synchronisation traffic, which is separated from the regular memory traffic. A single-stage combining network has several advantages: (1) It is very cost effective because only one stage is needed (instead of logN stages). (2) Only one network is needed to handle both forward and returning requests. (3) All synchronisation traffic is confined to a single stage;hence, packets have more opportunities to combine. (4) Combined requests are distributed evenly through the network;the wait buffer site is reduced. (5) Fast-finishing algorithms [18] can be used to shorten the network delay. Because of all these advantages, we show that a single-stage combining network gives good performance at a lower cost than a multistage combining network. © 1991 IEEE.

关键词： Synchronization

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SUPERCOMPUTER PERFORMANCE EVALUATION AND THE PERFECT BENCHMARKS 90

SUPERCOMPUTER PERFORMANCE EVALUATION AND THE PERFECT BENCHMA...

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1990 INTERNATIONAL CONF ON supercomputing

作者： CYBENKO, G KIPP, L POINTER, L KUCK, D Center for Supercomputing Research and Development University of Illinois at Urbana Champaign 305 Talbot Lab 104 S. Wright St. Urbana IL

ISBN: (纸本)0897913698

In the past three years, the Perfect BenchmarkTM Suite has evolved from a supercomputer performance evaluation plan, presented by Kuck and Sameh at the 1987 International Conference on supercomputing, to a vigorous international activity. This paper surveys the current state of this supercomputer performance evaluation effort with particular focus on the adopted methodology. While there has been considerable success in achieving the goals of the plan, some issues remain unresolved, and new questions have surfaced.

关键词： Computers, Supercomputer

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