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Using memory in the Cedar system 1st

1st International Conference on supercomputing, 1987

作者： McGrath, Robert E. Emrath, Perry A. Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 104 South Wright Street UrbanaIL61801 United States

ISBN: (纸本)9783540189916

The design of the virtual memory system for the Cedar multiprocessor under construction at the University of Illinois is discussed. The Cedar architecture features a hierarchy of memory, some shared by all processors, and some shared by subsets of processors. The Xylem operating system is based on Alliant Computer Systems CONCENTRIXTM operating system, which is based on 4.2BSD UNIXTM. Xylem supports multi-tasking and demand paging of parts of the memory hierarchy into a linear virtual address space. Memory may be private to a task or shared between all the tasks. The locality and attributes of a page may be modified during the execution of a program. Examples of how these mechanisms can be used are discussed. © 1988, Springer-Verlag.

关键词： Virtual addresses

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PARCEL: Project for the automatic restructuring and concurrent evaluation of lisp 88

PARCEL: Project for the automatic restructuring and concurre...

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2nd International Conference on supercomputing, ICS 1988

作者： Harrison, Luddy Padua, David A. Center for Supercomputing Research and Development Department of Computer Science University of Illinois at Urbana-Champaign UrbanaIL61801 United States

ISBN: (纸本)0897912721

Parcel (Project for the Automatic Restructuring and Concurrent Evaluation of Lisp) is an investigation of the problem of compiling Lisp for evaluation on a shared memory multiprocessor. In this paper, we present an overview of the process of compilation in Parcel. This process consists, broadly, of an interprocedural analysis, followed by a function-level restructuring of the lambda expressions that constitute a program. We discuss both of these phases, and illustrate the steps of restructuring with a few examples. A novel representation for s-expressions is employed in Parcel, to facilitate the parallel creation and access of lists;we review this representation, and discuss its implications for the compilation process. We conclude with some preliminary performance measurements of the prototypes of the Parcel compiler and run-time system. © 1988 ACM.

关键词： Program compilers

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APPLICATION OF KRYLOV EXPONENTIAL PROPAGATION TO FLUID-DYNAMICS EQUATIONS

APPLICATION OF KRYLOV EXPONENTIAL PROPAGATION TO FLUID-DYNAM...

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10TH CONF ON COMPUTATIONAL FLUID DYNAMICS

作者： SAAD, Y SEMERARO, BD Research Institute for Advanced Computer Science (RIACS) NASA Ames Research Center Moffett Field 94035 CA United States Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana 61801 Il United States

In this paper we present an application of matrix exponentiation via Krylov subspace projection, to the solution of fluid dynamics problems. The main idea is to approximate the operation exp(A)v by means of a projection-like process onto a Krylov subspace. This results in a computation of an exponential matrix vector product similar to the one above but of a much smaller size. Time integration schemes can then be devised to exploit this basic computational kernel. The motivation of this approach is to provide timeintegration schemes that are essentially of an explicit nature but which have good stability properties. © 1991 by the American Institute of Aeronautics, and Astronautics, Inc. All rights reserved.

关键词： Fluid dynamics

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An efficient approach to computing fixpoints for complex program analysis 94

An efficient approach to computing fixpoints for complex pro...

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8th International Conference on supercomputing, ICS 1994

作者： Chen, Li-Ling Harrison, Williams Ludwell Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street UrbanaIL61801 United States

ISBN: (纸本)0897916654

A chief source of inefficiency in program analysis using abstract interpretation comes from the fact that a large context (i.e., problem state) is propagated from node to node during the course of an analysis. This problem can be addressed and largely alleviated by a technique we call contezt projection, which projects an input context for a node to the portion that is actually relevant and determines whether the node should be reevaluated based on the projected context. This technique reduces the cost of an evaluation and eliminates unnecessary evaluations. Therefore, the efficiency of computing fixpoints over general lattices is greatly improved. A specific method, reachability, is presented as an example to accomplish context projection. Experimental results using reachability show very convincing speedups (more than eight for larger programs) that demonstrate the practical significance of context projection. © 1994 ACM.

关键词： Abstracting

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Parallel discrete event simulation on shared-memory multiprocessors 24

Parallel discrete event simulation on shared-memory multipro...

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24th Annual Symposium on Simulation, ANSS 1991

作者： Konas, Pavlos Yew, Pen-Chung Center for Supercomputing Research and Development 305 Talbot Laboratory 104 S. Wright Street UrbanaIL61801 United States

ISBN: (纸本)0818621699

This paper describes the implementation and the performance study of three parallel discrete event simulation methods on a shared memory machine. These methods, which share a single user interface, include the Chandy-Misra paradigm with deadlock avoidance;the Time Warp approach with direct, aggressive, and lazy cancellation;and a hybrid approach, which exploits the parallelism available at each point in simulated time. In this study we also examine the impact of task-partitioning and of processor self-scheduling on the efficient implementation of the above methods. Two kinds of systems are simulated: a synchronous multiprocessor machine and an asynchronous toroid network with FCFS server nodes. The performance of the implemented methods is discussed, and conclusions are drawn from the obtained results. © 1991 IEEE.

关键词： User interfaces

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FPGA and ARM processor based supercomputing

FPGA and ARM processor based supercomputing

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2018 International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2018

作者： Akram, Wasim Hussain, Tassadaq Ayguade, Eduard Riphah International University Islamabad Pakistan Unal Color of Education Research and Development Islamabad Pakistan Barcelona Supercomputing Center Barcelona Spain

ISBN: (纸本)9781538613702

The low-cost and low-power heterogeneous architecture platform such as Xilinx Zynq SoC provides an extensive combination of ARM multi-core processor with FPGA accelerator for acceleration of high performance computing applications. In this paper, we proposed an FPGA and ARM processor based supercomputer system composed of five Zynq SoCs compute-nodes. The design system uses message passing interface libraries for communication between compute-nodes while AXI4-stream interfaces between ARM processor and FPGA inside a compute-node. An FIR filter application is used to test the performance of the system with and without FPGA accelerators. The results show that the performance of ARM based supercomputer with FPGA accelerators is 8.56 times higher than similar system without FPGA accelerators. © 2018 IEEE.

关键词： Field programmable gate arrays (FPGA)

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The interprocedural analysis and automatic parallelization of Scheme programs

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Lisp and Symbolic Computation 1989年第3-4期2卷 179-396页

作者： Harrison III, Williams Ludwell Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 305 Talbot Laboratory Urbana 61801 IL 104 South Wright Street United States

Lisp and its descendants are among the most important and widely used of programming languages. At the same time, parallelism in the architecture of computer systems is becoming commonplace. There is a pressing need to extend the technology of automatic parallelization that has become available to Fortran programmers of parallel machines, to the realm of Lisp programs and symbolic computing. In this paper we present a comprehensive approach to the compilation of Scheme programs for shared-memory multiprocessors. Our strategy has two principal components:interprocedural analysis and program restructuring. We introduce procedure strings and stack configurations as a framework in which to reason about interprocedural side-effects and object lifetimes, and develop a system of interprocedural analysis, using abstract interpretation, that is used in the dependence analysis and memory management of Scheme programs. We introduce the transformations of exit-loop translation and recursion splitting to treat the control structures of iteration and recursion that arise commonly in Scheme programs. We propose an alternative representation for s-expressions that facilitates the parallel creation and access of lists. We have implemented these ideas in a parallelizing Scheme compiler and run-time system, and we complement the theory of our work with "snapshots" of programs during the restructuring process, and some preliminary performance results of the execution of object codes produced by the compiler. © 1989 Kluwer Academic Publishers.

关键词： Automatic Parallelization Interprocedural Analysis Abstract Interpretation Lisp Parallel Processing Program Transformation Scheme Symbolic Computation

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A version control approach to cache coherence 89

A version control approach to cache coherence

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3rd International Conference on supercomputing, ICS 1989

作者： Cheong, Hoichi Veidenbaum, Alex Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 104 South Wright Street UrbanaIL61801 United States

ISBN: (纸本)0897913094

A version control approach to maintain cache coherence is proposed for large-scale shared-memory multiprocessor systems with interconnection networks. The new approach, unlike existing approaches for such class of systems, makes it possible to exploit temporal locality across synchronization boundaries. As with the other software-directed approaches, each processor independently manages its cache, i.e., there is no interprocessor communication involved in maintaining cache coherence. The hardware required per processor in the version control approach stays constant as the number of processors increases;hence, it scales up to larger systems. Furthermore, the new approach incurs low overhead. The simulated results of several schemes for large-scale systems show that the new approach achieves a data cache hit ratio closest to maximum possible. © 1989 ACM.

关键词： Large scale systems

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Multithreading runtime support for loop and functional parallelism 2nd

Multithreading runtime support for loop and functional paral...

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2nd International Symposium on High Performance Computing, ISHPC 1999

作者： Saito, Hideki Stavrakos, Nicholas Polychronopoulos, Constantine Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St UrbanaIL61801 United States

ISBN: (纸本)3540659692

This paper presents a multithreading runtime library that provides unified support for loop and functional parallelisms. It implements a queue-based dynamic load-balancing scheme to exploit arbitrarily nested or disjointed parallel constructs, while keeping its overhead competitive with simpler conventional libraries. The library also provides support for the recently adopted industry standard: OpenMP. © 1999, Springer-Verlag. All rights reserved.

关键词： Application programming interfaces (API)

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Toward auto-scheduling compilers

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The Journal of supercomputing 1988年第3期2卷 297-330页

作者： Polychronopoulos, Constantine D. Center for Supercomputing Research and Development and Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana 61801 Il 104 South Wright Street United States

In this paper we propose a general framework for compiling, scheduling, and executing parallel programs on parallel computers. We discuss important aspects of program partitioning, scheduling, and execution, and consider possible realistic alternatives for each issue. Subsequently we propose a possible implementation of an auto-scheduling compiler and give simple examples to illustrate the principles. Our approach to the entire problem is to utilize program information available to the compiler while, at the same time, allowing for run-time "corrections" and flexibility. © 1988 Kluwer Academic Publishers.

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