检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

24 篇 期刊文献
24 篇 会议

馆藏范围

48 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

24 篇 工学
- 11 篇 计算机科学与技术...
- 6 篇 软件工程
- 5 篇 信息与通信工程
- 3 篇 材料科学与工程（可...
- 3 篇 电气工程
- 2 篇 生物工程
- 1 篇 力学（可授工学、理...
- 1 篇 冶金工程
- 1 篇 动力工程及工程热...
- 1 篇 电子科学与技术（可...
- 1 篇 控制科学与工程
- 1 篇 测绘科学与技术
- 1 篇 化学工程与技术
- 1 篇 航空宇航科学与技...
- 1 篇 环境科学与工程（可...
- 1 篇 安全科学与工程
22 篇 理学
- 9 篇 数学
- 6 篇 物理学
- 4 篇 统计学（可授理学、...
- 3 篇 生物学
- 2 篇 化学
- 2 篇 地球物理学
- 1 篇 地理学
- 1 篇 系统科学
9 篇 管理学
- 6 篇 管理科学与工程(可...
- 6 篇 工商管理
- 2 篇 图书情报与档案管...
3 篇 经济学
- 3 篇 应用经济学
1 篇 教育学
- 1 篇 教育学
- 1 篇 心理学(可授教育学...
1 篇 医学

主题

3 篇 computer science
3 篇 libraries
3 篇 concurrent compu...
3 篇 research and dev...
3 篇 laboratories
3 篇 logic circuits
2 篇 circuit simulati...
2 篇 message passing
2 篇 application soft...
2 篇 privatization
2 篇 parallel program...
2 篇 processor schedu...
2 篇 embedded computi...
2 篇 hardware
2 篇 scheduling
1 篇 pulsars
1 篇 parallel algorit...
1 篇 reed-solomon cod...
1 篇 protein engineer...
1 篇 performance gain

机构

5 篇 leeds institute ...
5 篇 center for psych...
5 篇 department of in...
5 篇 institute for pa...
5 篇 department of st...
5 篇 university of pi...
5 篇 arnie charbonnea...
5 篇 ilsbio llc bioba...
5 篇 department of mo...
5 篇 osaka internatio...
5 篇 research departm...
5 篇 department of ve...
5 篇 royal stoke univ...
5 篇 biomedical engin...
5 篇 department of ex...
5 篇 victorian instit...
5 篇 research core ce...
5 篇 department of bi...
5 篇 institute of cli...
5 篇 institute of com...

作者

3 篇 padua david
2 篇 kleinheinz korti...
2 篇 weatherford step...
2 篇 alexandru nicola...
2 篇 moreira josé e.
2 篇 arun kejariwal
2 篇 eigenmann rudolf
2 篇 schlesner matthi...
2 篇 faigin keith
2 篇 korbel jan o.
2 篇 hoeflinger jay
2 篇 polychronopoulos...
2 篇 constantine d. p...
2 篇 banerjee utpal
2 篇 rauchwerger lawr...
2 篇 imielinski marci...
2 篇 tu peng
2 篇 getz gad
2 篇 grout john
2 篇 beroukhim rameen

语言

44 篇 英文
3 篇 其他
1 篇 中文

检索条件"机构=Center for Supercomputing Research and Development and Coordinated Science Laboratory"

共 48 条记录，以下是21-30 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links

Impact of DFE Error Propagation on FEC-Based High-Speed I/O ...

引用

GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference

作者： Rajan Narasimha Nirmal Warke Naresh Shanbhag Coordinated Science Laboratory/ECE Department University of Illinois Urbana-Champaign Urbana IL USA DSPS Research and Development Center Texas Instruments Inc. Dallas TX USA

Modern state-of-the-art I/O links today rely exclusively upon a high SNR channel and an equalization-based inner transceiver to achieve a BER of 10 -15 . The equalizer typically consists of a transmit pre-emphasis driver for pre-cursor equalization and a receive DFE for post-cursor cancellation. Recently, forward error-correction (FEC) coding has been proposed to improve the BER and reduce power in high-speed I/O links. However, error-propagation in the DFE is a significant issue affecting code performance. The link performance is also tied to FEC implementation parameters like degree of parallelism. This paper presents a framework for analyzing the impact of DFE burst errors and implementation parameters on end-to-end link performance. For 10.3125 Gb/s transmission through a channel with 19 dB loss at Nyquist rate and serial FEC implementation, we find that a code rate r = 0.8 gives the best ISI penalty vs coding gain trade-off, and a codeword length of 750 bits is necessary to meet target performance. Further, it is observed that the performance of burst error correction codes does not necessarily improve with codeword length, i.e., there is an BER-optimal block length at a given code rate.

关键词： Decision feedback equalizers Forward error correction Bit error rate Transceivers Performance analysis Propagation losses Intersymbol interference Performance gain Performance loss Error correction codes

来源：评论

学校读者我要写书评

暂无评论

Segmentation of multivariate mixed data via lossy coding and compression

Segmentation of multivariate mixed data via lossy coding and...

引用

Visual Communications and Image Processing 2007

作者： Derksen, Harm Yi, Ma. Hong, Wei Wright, John Department of Mathematics University of Michigan United States Coordinated Science Laboratory University of Illinois Urbana Champaign United States DSP Solutions Research and Development Center Texas Instruments

ISBN: (纸本)0819466212

In this paper, based on ideas from lossy data coding and compression, we present a simple but surprisingly effective technique for segmenting multivariate mixed data that are drawn from a mixture of Gaussian distributions or linear subspaces. The goal is to find the optimal segmentation that minimizes the overall coding length of the segmented data, subject to a given distortion. We show that deterministic segmentation minimizes an upper bound on the (asymptotically) optimal solution. The proposed algorithm does not require any prior knowledge of the number or dimension of the groups, nor does it involve any parameter estimation. Simulation results reveal intriguing phase-transition behaviors of the number of segments when changing the level of distortion or the amount of outliers. Finally, we demonstrate how this technique can be readily applied to segment real imagery and bioinformatic data. © 2007 SPIE-IS&T.

关键词： Image segmentation

来源：评论

学校读者我要写书评

暂无评论

History-aware Self-Scheduling

History-aware Self-Scheduling

引用

International Conference on Parallel Processing (ICPP)

作者： Arun Kejariwal Alexandru Nicolau Constantine D. Polychronopoulos Center for Embedded Computer Systems School of Information and Computer Science University of California Irvine USA Center of Supercomputing Research & Development Computer and Systems Research Laboratory University of Illinois Urbana-Champaign USA

Scheduling parallel loops, i.e., the way iterations are mapped on to different processors, plays a critical role in the efficient execution of programs, particularly of super-computing applications, on multiprocessor systems. In applications where the problem dimension (and hence execution time) is dependent on run-time data, loop iterations also tend to be of variable length - this variability affects both sequential and parallel loops and in particular nested loops and it is quite prevalent in sparse matrix solvers. In this paper, we propose a (execution) history-aware self-scheduling approach of irregular parallel loops on heterogeneous multiprocessor systems. First, the proposed method computes the chunk size, i.e., the amount of work allocated to a processor at each scheduling step, based on the variance in workload distribution across the iteration space. Second, it fine tunes the chunk size based on the execution history of the loop, wherein the workload of an iteration is determined at run-time based on the statistical deviation of workload estimates of previously executed iterations from their corresponding actual workloads. We evaluate our techniques using a set of kernels (extracted from industry-strength SPEC OMPM 2001 benchmark) with uneven workload distributions. The results show that our technique performs 5% -18% better than the existing schemes

关键词： Optimal scheduling Multiprocessing systems Runtime Concurrent computing Processor scheduling Finishing Embedded computing Distributed computing Protein engineering Dynamic scheduling

来源：评论

学校读者我要写书评

暂无评论

An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications

An adaptive multi-module cache with hardware prefetching mec...

引用

Euromicro Conference on Parallel, Distributed and Network-Based Processing

作者： J.-H. Lee G.-H. Park Shin-Dug Kim Supercomputing Laboratory Department of Computer Science Yonsei University Seoul South Korea SOC Research and Development Center System LSI Business Samsung Electronics Company Limited Suwon South Korea

This research is to design a high performance cache structure with a hardware prefetching mechanism that is applicable to embedded multimedia processors. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. The overhead of prefetching operation is shown to be a negligible factor. Also the accuracy of the prefetch operation is over 97% of the total number of prefetches generated. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with four or twice as much space respectively. And also, compared with a victim cache with 32-byte block size, the average miss ratio can be reduced by over twice for multimedia applications. We have also shown that power consumption in the AMMC is around 10% /spl sim/ 60% lower than these various cache systems.

关键词： Hardware Prefetching Energy consumption Application software Multimedia systems Signal generators Power generation Laboratories Computer science research and development

来源：评论

学校读者我要写书评

暂无评论

Effective cross-platform, multilevel parallelism via dynamic adaptive execution 16

Effective cross-platform, multilevel parallelism via dynamic...

引用

16th International Parallel and Distributed Processing Symposium, IPDPS 2002

作者： Ko, W. Yankelevsky, M. Nikolopoulos, D.S. Polychronopoulos, C.D. Center for Supercomputing Research and Development Coordinated Science Laboratory University of Illinois at Urbana-Champaign 1308 West Main St. UrbanaIL61801 United States

ISBN: (纸本)0769515738

This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical architectures. Using the NAS parallel benchmarks, we first illustrate the lack of portable performance on state-of-the-art scalable parallel systems despite the use of two portable programming models, MPI and OpenMP. Then we present a dynamic compilation and execution framework that provides the desired portability through the use of program slices. These slices are used to select the optimal program decomposition on each architecture. Currently, our framework uses a simple incremental algorithm, which effectively identifies single or multi-level program decompositions that maximize performance. This algorithm can be used as a rule of thumb for automatic multilevel parallelization. The effectiveness of the approach is demonstrated on the NAS benchmarks running on two architectural platforms. © 2002 IEEE.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Effective cross-platform, multilevel parallelism via dynamic adaptive execution

Effective cross-platform, multilevel parallelism via dynamic...

引用

International Symposium on Parallel and Distributed Processing (IPDPS)

作者： W. Ko M. Yankelevsky D.S. Nikolopoulos C.D. Polychronopoulos Center for Supercomputing Research and Development Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana-Champaign IL USA

This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical architectures. Using the NAS parallel benchmarks, we first illustrate the lack of portable performance on stateof- the-art scalable parallel systems despite the use of two portable programming models, MPI and OpenMP. Then we present a dynamic compilation and execution framework that provides the desired portability through the use of program slices. These slices are used to select the optimal program decomposition on each architecture. Currently, our framework uses a simple incremental algorithm, which effectively identifies single or multi-level program decompositions that maximize performance. This algorithm can be used as a rule of thumb for automatic multilevel parallelization. The effectiveness of the approach is demonstrated on the NAS benchmarks running on two architectural platforms.

关键词： Hardware Parallel programming Uncertainty Optimization methods Dynamic compiler research and development Thumb Topology Delay Libraries

来源：评论

学校读者我要写书评

暂无评论

FALCON: A MATLAB interactive restructuring compiler 8th

FALCON: A MATLAB interactive restructuring compiler

引用

Proceedings of the 1995 8th International Workshop on Languages and Compilers for Parallel Computing

作者： De, Rose, L. Gallivan, K. Gallopoulos, E. Marsolf, B. Padua, D. Center for Supercomputing Research Development and Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana 61801 IL United States

ISBN: (纸本)9783540607656

The development of efficient numerical programs and library routines for high-performance parallel computers is a complex task requiring not only an understanding of the algorithms to be implemented, but also detailed knowledge of the target machine and the software environment. In this paper, we describe a programming environment that can utilize such knowledge for the development of high-performance numerical programs and libraries. This environment uses an existing highlevel array language (MATLAB) as source language and performs static, dynamic, and interactive analysis to generate Fortran 90 programs with directives for parallelism. It includes capabilities for interactive and automatic transformations at both the operation-level and the functional- or algorithm-level. Preliminary experiments, comparing interpreted MATLAB programs with their compiled versions, show that compiled programs can perform up to 48 times faster on a serial machine, and up to 140 times faster on a vector machine. © Springer-Veriag Berlin Heidelberg 1996.

关键词： MATLAB

来源：评论

学校读者我要写书评

暂无评论

Restructuring programs for high-speed computers with Polaris

Restructuring programs for high-speed computers with Polaris

引用

1996 ICPP Workshop on Challenges for Parallel Processing, ICPPW 1996

作者： Blume, Bill Eigenmann, Rudolf Faigin, Keith Grout, John Lee, Jaejin Lawrence, Tom Hoeflinger, Jay Padua, David Paek, Yunheung Petersen, Paul Pottenger, Bill Rauchwerger, Lawrence Tu, Peng Weatherford, Stephen Center for Supercomputing Research and Development Coordinated Science Laboratory University of Illinois at Urbana-Champaign 1308 West Main Street UrbanaIL61801-2307 United States

ISBN: (纸本)081867623X

The ability to automatically parallelize standard programming languages results in program portability across a wide range of machine architectures. It is the goal of the Polaris project to develop a new parallelizing compiler that overcomes limitations of current compilers. While current parallelizing compilers may succeed on small kernels, they often fail to extract any meaningful parallelism from whole applications. After a study of application codes, it was concluded that by adding a few new techniques to current compilers, automatic parallelization becomes feasible for a range of whole applications. The techniques needed are interprocedural analysis, scalar and array privatization, symbolic dependence analysis, and advanced induction and reduction recognition and elimination, along with run-time techniques to permit the parallelization of loops with unknown dependence relations. © 1996 IEEE.

关键词： Privatization

来源：评论

学校读者我要写书评

暂无评论

A MATLAB to Fortran 90 translator and its effectiveness 96

A MATLAB to Fortran 90 translator and its effectiveness

引用

Proceedings of the 10th international conference on supercomputing

作者： Luiz De Rose David Padua Center for Supercomputing Research and Development Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana Illinois

来源：评论

学校读者我要写书评

暂无评论

Restructuring programs for high-speed computers with Polaris

Restructuring programs for high-speed computers with Polaris

引用

International Conference on Parallel Processing Workshops (ICPPW)

作者： Blume Eigenmann Faigin Grout Jaejin Lee Lawrence Hoeflinger Padua Yunheung Paek Petersen Pottenger Rauchwerger Peng Tu Weatherford Center for Supercomputing Research and Development Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

关键词： Program compilers Parallel programming

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共5页 << < 1 2 3 4 5 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：