检索结果-内蒙古大学图书馆

Detailed and clock-driven simulation for HPC interconnection network

Frontiers of Computer Science 2016年第5期10卷 797-811页

作者： Wenhao ZHOU Juan CHEN Chen CUI Qian WANG Dezun DONG Yuhua TANG State Key Laboratory of High Performance Computing School of Computer National University of Defense Technology Changsha 410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China

performance and energy consumption of high performance computing （HPC） interconnection networks have a great significance in the whole supercomputer, and building up HPC interconnection network simulation plat- form is very important for the research on HPC software and hardware technologies. To effectively evaluate the per- formance and energy consumption of HPC interconnection networks, this article designs and implements a detailed and clock-driven HPC interconnection network simulation plat- form, called HPC-NetSim. HPC-NetSim uses application- driven workloads and inherits the characteristics of the de- tailed and flexible cycle-accurate network simulator. Besides, it offers a large set of configurable network parameters in terms of topology and routing, and supports router＇s on/off states. We compare the simulated execution time with the real execution time of Tianhe-2 subsystem and the mean error is only 2.7%. In addition, we simulate the network behaviors with different network structures and low-power modes. The results are also consistent with the theoretical analyses.

关键词： high performance computing clock-driven sim-ulation interconnection network BookSim

来源：评论

学校读者我要写书评

暂无评论

Untrusted Hardware Causes Double-Fetch Problems in the I/O Memory

引用

Journal of Computer Science & Technology 2018年第3期33卷 587-602页

作者： Kai Lu Peng-Fei Wang Gen Li Xu Zhou College of Computer National University of Defense Technology Changsha 410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China Collaborative Innovation Center of High-Performance Computing National University of Defense Technology Changsha 410073 China

The double fetch problem occurs when the data is maliciously changed between two kernel reads of the supposedly same data, which can cause serious security problems in the kernel. Previous research focused on the double fetches between the kernel and user applications. In this paper, we present the first dedicated study of the double fetch problem between the kernel and peripheral devices （aka. the hardware double fetch）. Operating systems communicate with peripheral devices by reading from and writing to the device mapped I/O （input and output） memory. Owing to the lack of effective validation of the attached hardware, compromised hardware could flip the data between two reads of the same I/O memory address, causing a double fetch problem. We propose a static pattern-matching approach to identify the hardware double fetches from the Linux kernel. Our approach can analyze the entire kernel without relying on the corresponding hardware. The results are categorized and each category is analyzed using case studies to discuss the possibility of causing bugs. We also find four previously unknown double-fetch vulnerabilities, which have been confirmed and fixed after reporting them to the maintainers.

关键词： hardware double fetch double-fetch bug I/O memory peripheral device double-fetch vulnerability

来源：评论

学校读者我要写书评

暂无评论

DFTracker: detecting double-fetch bugs by multi-taint parallel tracking

引用

Frontiers of Computer Science 2019年第2期13卷 247-263页

作者： Pengfei WANG Kai LU Gen LI Xu ZHOU Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China Collaborative Innovation Center of High Performance Computing National University of Defense Technology Changsha 410073 China

A race condition is a common trigger for concurrency bugs. As a special case, a race condition can also occur across the kernel and user space causing a doublefetch bug, which is a field that has received little research attention. In our work, we first analyzed real-world doublefetch bug cases and extracted two specific patterns for doublefetch bugs. Based on these patter ns, we proposed an approach of multi-taint parallel tracking to detect double-fetch bugs. We also implemented a prototype called DFTracker (doublefetch bug tracker), and we evaluated it with our test suite. Our experiments demonstrated that it could effectively find all the double-fetch bugs in the test suite including eight realworld cases with no false negatives and minor false positives. In addition, we tested it on Linux kernel and found a new double-fetch bug. The execution overhead is approximately 2x for single-file cases and approximately 9x for the whole kernel test, which is acceptable. To the best of the authors1 knowledge, this work is the first to introduce multi-taint parallel tracking to double-fetch bug detection—an innovative method that is specific to double-fetch bug features—and has better path coverage as well as lower runtime overhead than the widely used dynamic approaches.

关键词： multi-taint parallel tracking double fetch race condition between kernel and user time of check to time of use real-world case analysis Clang Static Analyzer

来源：评论

学校读者我要写书评

暂无评论

A mathematical model for empowerment of Beowulf clusters for exascale computing

A mathematical model for empowerment of Beowulf clusters for...

引用

2013 11th International Conference on high performance computing and Simulation, HPCS 2013

作者： Mirtaheri, Seyedeh Leili Khaneghah, Ehsan Mousavi Grandinetti, Lucio Sharifi, Mohsen Center of High Performance Computing for Parallel and Distributed Processing University of Calabria Rende Italy School of Computer Engineering Iran University of Science and Technology Tehran Iran

ISBN: (纸本)9781479908363

high-performance computing (HPC) clusters are currently faced with two major challenges - namely, the dynamic nature of new generation of applications and the heterogeneity of platforms - if they are going to be useful for exascale computing. Processes running these applications may well demand unpredictable requirements and changes to system configuration and capabilities at runtime, thereby requiring fast system response without sacrificing the transparency and integrity of the reconfigured empowered system that is running on a heterogeneous platform. While a challenge in and of itself, platform heterogeneity is both useful and instrumental in the handling of unpredictable requests. The realization of such a dynamically reconfigurable and heterogeneous HPC cluster system for exascale computing requires a model to guide running processes to determine if they need empowerment of the current cluster, and if yes, by how much. To show the feasibility of empowerment of traditional HPC clusters for exascale computing, we have selected Beowulf as a noble candidate cluster and present a mathematical model for the empowerment of Beowulf clusters for exascale computing (EBEC). We have developed the model in line with Beowulf's cluster approach and by using vector space algebra. In contrast to traditional hardware-oriented approaches to improvise the performance of clusters, we use a software approach to the development of the proposed model by emphasizing processes, which act as the creators of the cluster and thus should decide on system (re)configuration, as the principal building blocks of the system. We have also adopted a new approach to heterogeneity by considering heterogeneity at different levels including hardware, system software, application software, and system functionality. In addition to support for heterogeneity and dynamic reconfiguration, the proposed model includes support for scalability that is crucial to exascale computing too. © 2013 IEEE.

关键词： Vector spaces

来源：评论

学校读者我要写书评

暂无评论

Galaxyfly: A novel family of flexible-radix low-diameter topologies for large-scales interconnection networks 16

Galaxyfly: A novel family of flexible-radix low-diameter top...

引用

30th International Conference on Supercomputing, ICS 2016

作者： Lei, Fei Dong, Dezun Liao, Xiangke Su, Xing Li, Cunlu National Laboratory for Parallel and Distributed Processing Collaborative Innovation Center of High Performance Computing College of Computer National University of Defense Technology Changsha410073 China

ISBN: (纸本)9781450343619

Interconnection network plays an essential role in the architecture of large-scale high performance computing (HPC) systems. In the paper, we construct a novel family of lowdiameter topologies, Galaxyfly, using techniques of algebraic graphs over finite fields. Galaxyfly is guaranteed to retain a small constant diameter while achieving a flexible tradeoff between network scale and bisection bandwidth. Galaxyfly lowers the demands for high radix of network routers and is able to utilize routers with merely moderate radix to build exascale interconnection networks. We present effective congestion-aware routing algorithms for Galaxyfly by exploring its algebraic property. We conduct extensive simulations and analysis to evaluate the performance, cost and power consumption of Galaxyfly against state-of-the-art topologies. The results show that our design achieves better performance than most existing topologies under various routing algorithms and traffic patterns, and is cost-effective to deploy for exascale HPC systems. © 2016 ACM.

关键词： Topology

来源：评论

学校读者我要写书评

暂无评论

Exploiting contention and congestion aware switch allocation in network-on-chips 17

Exploiting contention and congestion aware switch allocation...

引用

50th ACM Turing Conference - China, ACM TUR-C 2017

作者： Li, Cunlu Dongy, Dezun Liao, Xiangke National Laboratory for Parallel and Distributed Processing Collaborative Innovation Center of High Performance Computing College of Computer National University of Defense Technology Changsha Hunan410073 China

ISBN: (纸本)9781450348737

Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting congestion and contention information to load balance the traffic. However, most prior works do not consider balancing the traffic load during switch allocation. Due to the lack of congestion information in switch allocation stage, switch allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of switch. In this paper, we propose to add the congestion and contention information into the switch allocation process and design an efficient on-chip switching strategy which utilizes the contention and congestion information to load balance the traffic and achieve efficient switch allocation. To further enhance the performance of our design, we carefully design our switch allocation strategy to balance the trade-off between traffic load balance and the matching efficiency in switch allocation. We evaluate our design under synthetic traffic and trace of parsec benchmarks. Our evaluations show this mechanism achieves optimal latency compared to best previous switch allocation strategies. © 2017 ACM.

关键词： Network-on-chip

来源：评论

学校读者我要写书评

暂无评论

high performance Interconnect Network for Tianhe System

引用

Journal of Computer Science & Technology 2015年第2期30卷 259-272页

作者：廖湘科庞征王克非卢宇彤谢旻夏军董德尊所光 College of Computer National University of Defense Technology Changsha 410073 Science and Technology on Parallel and Distributed Processing Laboratory National Changsha 410073 China China University of Defense Technology State Key Laboratory of High Performance Computing National University of Defense Technology Changsha 410073 China

In this paper, we present the Tianhe-2 interconnect network and message passing services. We describe the architecture of the router and network interface chips, and highlight a set of hardware and software features effectively supporting high performance communications, ranging over remote direct memory access, collective optimization, hardwareenable reliable end-to-end communication, user-level message passing services, etc. Measured hardware performance results are also presented.

关键词： Tianhe-2 supercomputer interconnect network router architecture network interface architecture user-level message passing

来源：评论

学校读者我要写书评

暂无评论

Leveraging the Compute Power of Two HPC Systems for higher-Dimensional Grid-Based Simulations with the Widely-distributed Sparse Grid Combination Technique 23

Leveraging the Compute Power of Two HPC Systems for Higher-D...

引用

2023 International Conference for high performance computing, Networking, Storage and Analysis, SC 2023

作者： Pollinger, Theresa Van Craen, Alexander Niethammer, Christoph Breyer, Marcel Pflüger, Dirk Institute for Parallel and Distributed Systems Universität Stuttgart Stuttgart Germany High Performance Computing Center Universität Stuttgart Stuttgart Germany

ISBN: (纸本)9798400701092

Grid-based simulations of hot fusion plasmas are often severely limited by computational and memory resources;the grids live in four- to six-dimensional space and thus suffer the curse of dimensionality. However, high resolutions are required to fully capture the physics of interest. The sparse grid combination technique is a multi-scale method in which many anisotropically coarse resolved grids are used to approximate a fine-scale solution - -and it alleviates the curse of *** paper presents the core concepts of the widely-distributed combination technique, which allows us to use the compute power and memory of more than one HPC system for the same simulation. We apply the sparse grid combination technique to a six-dimensional advection problem serving as a proxy for plasma simulations. The full-grid solution approximated by the combination technique would contain ≈ 5 ZB if computed with conventional grid-based methods. Even the combination technique simulation operates on ≈ 1 × 1011 double-precision degrees of freedom, or 988 GB, plus the supporting sparse grid data structures. We propose a new approach to divide the compute load between the two HPC systems, requiring only 76 GB to be exchanged. Based on this, we have realized the first synchronous combination technique simulation using two HPC systems, in our case the two German Tier-0 supercomputers HAWK and SuperMUC-NG. On two systems, the simulation can be computed at an average overhead of ≈ 35 % (108 s per combination step) for file I/O and transfer. The presented concepts apply to any pair of HPC systems if high-speed data transfer is possible. © 2023 ACM.

关键词： Supercomputers

来源：评论

学校读者我要写书评

暂无评论

A resource broker for computing nodes selection in grid computing environments 3rd

引用

3rd International Conference on Grid and Cooperative computing, GCC2004

作者： Yang, Chao-Tung Lai, Chuan-Lin Shih, Po-Chi Li, Kuan-Ching High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung407 Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Shalu Taichung433 Taiwan

ISBN: (纸本)3540235647

As Grid computing is becoming a reality, there is a need for managing and monitoring the available resources worldwide, as well as the need for conveying these resources to the everyday user. This paper describes a resource broker with its main function as to match the available resources to the user’s needs. The use of the resource broker provides a uniform interface to access any of the available and appropriate resources using user’s credentials. The resource broker runs on top of the Globus Toolkit. Therefore, it provides security and current information about the available resources and serves as a link to the diverse systems available in the Grid. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Grid computing

来源：评论

学校读者我要写书评

暂无评论

Decision tree construction for data mining on grid computing environments

Decision tree construction for data mining on grid computing...

引用

19th International Conference on Advanced Information Networking and Applications, AINA 2005

作者： Yang, Chao-Tung Tsai, Shu-Tzu Li, Kuan-Ching High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung City 40704 Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung County 43301 Taiwan

ISBN: (纸本)0769522491

In this paper, we present our Grid-based decision tree architecture, with the intention of applying it to both parallel and sequential algorithms. Also, we show that, based on the scope and model of data mining applied in the Grid environment as well as user equivalent perspective, Grid roles can be categorized into three types. It is our goal, through these definitions, to help software developers define clear system processes and differentiate the application scope for software applications. To, fulfill our architecture, we first apply an existing parallel decision tree algorithm (the SPRINT algorithm) to the Grid environment. The performance and differences in many other areas are compared using datasets of different sizes. The experimental results will be used for future reference and further development. © 2005 IEEE.

关键词： Data mining

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：