Recently, Deep Learning (DL) approaches have been applied to solve the Sentiment Classification (SC) problem, which is a core task in reviews mining or Sentiment Analysis (SA). The performances of these approaches are...
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We provide a new model for texture synthesis based on a multiscale, multilayer feature extractor. Within the model, textures are represented by a set of statistics computed from ReLU wavelet coefficients at different ...
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This paper studies online optimization under inventory (budget) constraints. While online optimization is a well-studied topic, versions with inventory constraints have proven difficult. We consider a formulation of i...
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This paper studies online optimization under inventory (budget) constraints. While online optimization is a well-studied topic, versions with inventory constraints have proven difficult. We consider a formulation of i...
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This paper studies online optimization under inventory (budget) constraints. While online optimization is a well-studied topic, versions with inventory constraints have proven difficult. We consider a formulation of i...
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In this work, we present a second-order nonuniform time-stepping scheme for the time-fractional Allen-Cahn equation. We show that the proposed scheme preserves the discrete maximum principle, and by using the convolut...
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The specification of modeling and analysis of real-time and embedded systems (MARTE) is an extension of the unified modeling language (UML) in the domain of real-time and embedded systems. Even though MARTE time m...
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The specification of modeling and analysis of real-time and embedded systems (MARTE) is an extension of the unified modeling language (UML) in the domain of real-time and embedded systems. Even though MARTE time model offers a support to describe both discrete and dense clocks, the biggest effort has been put so far on the specifi- cation and analysis of discrete MARTE models. To address hybrid real-time and embedded systems, we propose to ex- tend statecharts using both MARTE and the theory of hybrid automata. We call this extension hybrid MARTE statecharts. It provides an improvement over the hybrid automata in that: the logical time variables and the chronometric time vari- ables are unified. The formal syntax and semantics of hybrid MARTE statecharts are given based on labeled transition sys- tems and live transition systems. As a case study, we model the behavior of a train control system with hybrid MARTE statecharts to demonstrate the benefit.
Central Processing Unit(CPU) scheduling is used to allocate CPU for multiple *** is one of the most important resources in the computer system,and its scheduling is vital and influential in operating ***,it is neces...
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ISBN:
(纸本)9781467349994
Central Processing Unit(CPU) scheduling is used to allocate CPU for multiple *** is one of the most important resources in the computer system,and its scheduling is vital and influential in operating ***,it is necessary to ensure the correctness of the CPU scheduling ***,testing the correctness of a scheduling program is difficult because it is hard to verify the correctness of its output,which is known as the test oracle problem in software *** Testing(MT) which has been recently proposed to alleviate the test oracle problem,is applied to test the CPU scheduling *** this paper,we use MT to test the Highest Response Ratio Next(HRRN) scheduling *** simulators of HRRN scheduler are used in the evaluation of our ***,some real life faults in one open source simulator are detected by *** experiments are performed based on mutants,and the experimental results show that MT is an effective strategy to test CPU scheduler.
The Clock Constraint Specification Language (CCSL) is a formal polychronous language based on the notion of logical clock. It defines a set of kernel constraints that can represent both asynchronous and synchronous re...
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ISBN:
(纸本)9781479921454
The Clock Constraint Specification Language (CCSL) is a formal polychronous language based on the notion of logical clock. It defines a set of kernel constraints that can represent both asynchronous and synchronous relations. It was originally developed as part of the UML Profile for MARTE to express causal and temporal constraints of Real-time and Embedded Systems. In this paper, we explore the use of CCSL for modeling scheduling requirements and to conduct schedulability analysis. For this purpose, a dedicated scheduling library of CCSL has been built. This library is endowed with a state-based operational semantics, and is applied to solve issues related to schedulability analysis and latency-insensitive design. We establish schedulability categories and latency-insensitiveness property in the context of the semantics, and solve those issues by using model checking techniques.
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