In this paper we present an application example for a run-time reconfigurable embedded system. The systemdesign is based on the perceptions of previous works from several groups. We comment on the theoretical backgro...
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In this paper we present an application example for a run-time reconfigurable embedded system. The systemdesign is based on the perceptions of previous works from several groups. We comment on the theoretical background of dynamic reconfiguration with respect to the embedded market and its special needs. Moreover a resource-efficient FPGA system and a first design is presented to serve as a basis for further work in the field of run-time reconfiguration applicable to the embedded market.
In this paper we present the hardware implementation of a Particle Filter for location estimation. Based on distance information to static network nodes, the filter estimates the three-dimensional position of a mobile...
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In this paper we present the hardware implementation of a Particle Filter for location estimation. Based on distance information to static network nodes, the filter estimates the three-dimensional position of a mobile network node. The design has been derived from a set of formal operation properties and synthesized for an FPGA prototype platform. Accessed through a serial interface, it can be used as a location estimation core from microcontrollers with low computational power. The implemented models for state transition and measurements can be re-parameterized during operation. Due to the chosen design approach these models can also easily be modified or exchanged in order to match the application needs. The correct functionality of the implementation has been shown using real time-of-flight based distance measurements. Therefore, the prototype platform has been integrated in an existing IEEE 802.15.4a compliant wireless network infrastructure.
This paper describes the implementation of an FPGA prototype of an application based on embedded ASIC technology. The overall goal is to implement a system that can monitor an Ethernet data stream and extracts configu...
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ISBN:
(纸本)9783981080162
This paper describes the implementation of an FPGA prototype of an application based on embedded ASIC technology. The overall goal is to implement a system that can monitor an Ethernet data stream and extracts configuration data marked by the EtherType field in the Ethernet header. For evaluation the application is implemented on a prototype consisting of two XILINX FPGA boards. Since the target platform is an ASIC with embedded reconfigurable architectures the prototype is divided in the corresponding parts. One board emulates the embedded reconfigurable architecture that contains the Ethernet MAC. Ethernet packets can reconfigure this MAC. The second board emulates the static part of the application that controls the reconfiguration process.
We propose a high level synthesis approach to generate RT level hardware from a specification of operation properties. The property language is called InTerval Language (ITL) and we assume the set of properties is com...
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ISBN:
(纸本)9789048193035
We propose a high level synthesis approach to generate RT level hardware from a specification of operation properties. The property language is called InTerval Language (ITL) and we assume the set of properties is complete, such that the properties alone are strong enough to map every possible sequence of input data to exactly one sequence of output data. A major advantage of using operation properties as a design method is the existence of commercial tools to check the completeness and consistency of the property set. Furthermore, operation properties are well suited for specifications of consecutive operations of finite length. We show the practicality of our method by implementing a particle filter for a localization application.
In this paper, we present a prototyping exercise, mapping a turbo decoder high-level description directly to FPGA for fast simulation of a software radio. The turbo decoder algorithm is described in C programming lang...
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In this paper, we present a prototyping exercise, mapping a turbo decoder high-level description directly to FPGA for fast simulation of a software radio. The turbo decoder algorithm is described in C programming language and the mapping has been done directly using the high level synthesis tool CoDeveloper. The manual transformations made on the code to facilitate efficient compilation and to achieve a tools compliant overall structure are described. The mapping exercise consists of several steps with changes resulting in improvements in performance and resource usage. The results in terms of effort of mapping and the achieved size and throughput are discussed.
This paper describes a tool extension named SpecScribe Analog for the specification-driven design of heterogeneous (analog and digital) systems. For SpecScribe a specification consists of atomic items called requireme...
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This paper describes a tool extension named SpecScribe Analog for the specification-driven design of heterogeneous (analog and digital) systems. For SpecScribe a specification consists of atomic items called requirements which can be hierarchically organized. These requirements can be translated to a more implementation like description using components or FSMs. The extension broadens the tool for the usage of hybrid automata. It allows the export of this requirement and implementation description to common languages like systemC(-AMS) or VHDL as well as to model checking languages like (hybrid-)SAL.
This paper presents a high-speed 4 bits full-flash Analog-to-Digital Converter for an UWB radar applications, implemented in 190 GHz SiGe BiCMOS technology. The ADC occupies 1.5 × 1.5 mm 2 , including bondpads. C...
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This paper presents a high-speed 4 bits full-flash Analog-to-Digital Converter for an UWB radar applications, implemented in 190 GHz SiGe BiCMOS technology. The ADC occupies 1.5 × 1.5 mm 2 , including bondpads. Converter has 6 GHz input bandwidth and operates up to 15 GSample/s. Power dissipation is 1 W including test buffers and 600 mW for a core part itself.
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