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23th International Conference on architecture of Computing Systems 2010, ARCS 2010

作者： Nowak, Fabian Kicherer, Mario Buchty, Rainer Karl, Wolfgang Chair for Computer Architecture Karlsruhe Institute of Technology Karlsruhe76128 Germany

ISBN: (纸本)9783800732227

With the advent of reconfigurable platforms and GPUs, we need means to successfully support the programmer and the system scheduler in efficiently exploiting the resources of the system. We present an approach of how the programmer can annotate the code so that a hardware abstraction layer can choose which resource to use for a given function call in a user-transparent manner. We evaluate the introduced toolchain and the time required to obtain these code annotations. © 2010 23th International Conference on architecture of Computing Systems 2010, ARCS 2010 - Workshop Proceedings. All rights reserved.

关键词： Abstracting

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Middleware support for transparent client-side caching

Middleware support for transparent client-side caching

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SC 2002, Workshop on Software Composition Affiliated with ETAPS 2002 (Satellite Event of ETAPS 2002)

作者： Pohl, Christoph Schill, Alexander Dresden University of Technology Institute for System Architecture Chair for Computer Networks Germany

This paper reflects on existing caching concepts in proxies and stubs of component technologies and lines out their advantages and deficiencies. A new concept is introduced that averts proliferation of component stubs on client side while transparently providing efficient caching of attributes that doesn't require any changes to existing code at all. Common object-oriented design facilities and code generation tools are leveraged to support seamless integration of these caching concepts into the development cycle. ©2002 Published by Elsevier Science B.V.

关键词： Middleware

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A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories 12

A Reference-less Sense Amplifier to Sense pA Currents in Fer...

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12th International Conference on Modern Circuits and Systems Technologies, MOCAST 2023

作者： Reuben, John Fey, Dietmar Slesazeck, Stefan Chair of Computer Architecture Erlangen Germany NaMLab GGmbH Dresden01187 Germany

ISBN: (纸本)9798350321074

Ferroelectric Tunnel Junction (FTJ) is an emerging non-volatile memory technology with increasing applications in memory and computing. Although the low currents of FTJ memories is an advantage from energy point of view, sensing of these memories is a challenge due to the pA read-out currents. In this work, we propose a Sense Amplifier (SA) specifically designed for FTJ memory technology. The proposed SA accumulates the charge at the gate of a read transistor and thus converts the pA current to hundreds of nA. A Schmitt-Trigger circuit is then used to differentiate between these two currents by using the threshold-voltage of the Schmitt-Trigger as reference. The proposed SA consumes an energy of 82 fJ/bit and also does not require an absolute voltage/current reference for sensing, thus conserving on-chip area. © 2023 IEEE.

关键词： Threshold voltage

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Intelligent Interactive Assistance and Mobile Multimedia Computing 1

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丛书名： Communications in computer and Information Science

1000年

作者： Djamshid Tavangarian Thomas Kirste Dirk Timmermann Ulrike Lucke Daniel Versick

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The smart miniFab: An industrial IoT demonstrator anywhere at any time 4th

The smart miniFab: An industrial IoT demonstrator anywhere a...

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4th International KES conference on Smart Education and Smart e-Learning, SEEL 2017

作者： Schubert, Tobias Völker, Benjamin Pfeifer, Marc Becker, Bernd Chair of Computer Architecture Faculty of Engineering Institute of Computer Science Albert-Ludwigs-University Freiburg Freiburg79110 Germany

ISBN: (纸本)9783319594507

The fourth industrial revolution is predicted to be one major topic in the upcoming decades, affecting nearly every industrial facility. The key enabler for the successful integration of corresponding developments are well-trained engineers with elaborated knowledge in the area of the Industrial Internet of Things (IIoT). This paper introduces a concept enabling engineering students to gain the required skills for the upcoming challenges connected with the fourth industrial revolution. Therefore, the Smart MiniFab was developed - a demonstrator of an industrial facility primed for the implementation and the analysis of different IIoT concepts on a small scale. Due to the modular structure of the system, students can use the demonstrator to programmatically implement the functionality of an entire facility from scratch or to test only certain new concepts. The hardware can be programmed via remote access from anywhere at any time, while live feedback is provided through a webcam and different other communication possibilities directly within the remote access application. While the Smart MiniFab was already the HW environment of different student projects, a new lab course is currently under development which enables the access to the Smart MiniFab for a broad number of students. © Springer International Publishing AG 2018.

关键词： Students

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IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures

IPAS: a design framework for analysis, synthesis and optimiz...

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作者： Hartmann, C. Häublein, K. Reichenbach, M. Fey, D. Chair of Computer Architecture University of Erlangen-Nuremberg Martensstr. 3 Erlangen91058 Germany

Recent trends in the image processing field have led to the use of more heterogeneous hardware architectures. The reason for this increase is that specialized cores, compared to standard CPUs, offer a more efficient way of achieving image processing applications. Specialized cores have less power, resource, and area consumption. On the other hand, designing such a heterogenous system with specialized cores is a challenging, error-prone and time-consuming task. Therefore, new frameworks are necessary for bringing an image processing application onto a given target platform by means of a tool chain. Some frameworks exist, but they do not address each need of a heterogeneous image processing application. Common weaknesses are (1) the low utilization of the image processing domain, (2) the inflexibility of the programming paradigms for different hardware architectures. Therefore, we define our own domain-specific design language called IPOL. To automate the derivation and optimization process, a synthesis tool named Image Processing architecture Synthesis was created. This tool will be the focus of this work. © 2016, Springer-Verlag Berlin Heidelberg.

关键词： Program processors

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An extended analysis of memory hierarchies for efficient implementations of image processing applications

An extended analysis of memory hierarchies for efficient imp...

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作者： Hartmann, Christian Fey, Dietmar Chair of Computer Architecture University of Erlangen-Nuremberg Martensstr. 3 Erlangen91058 Germany

Through continued miniaturization of electronic devices embedded smart cameras are steadily becoming more and more important. The reduction of the camera size increases the spectrum of applications. In industrial applications the range of smart cameras spans from quality monitoring and position tracking to the calibration of production machines. In non-professional applications a distinct boom in action cameras combined with fused sensor information can be observed. However, all of these applications have a common bottleneck: the memory architecture. Most image processing applications are memory-bound tasks. Thus, the amount of time for transferring data with image processing applications decisively affects the application’s entire processing time. Different memory access patterns require different memory configurations and hierarchies. An insufficient match between the image processing application and the memory architecture leads to a poor performance in the image processing system. This can lead to longer processing times, and larger energy consumption rates. This work introduces new methods of classifying image processing applications by using their memory access pattern for mapping on memory architectures. Our work combines a simulation framework the heterogenous memory simulator with a analytical framework the memory analyzer to find bottlenecks inside the image processing application and aids in finding a suitable, application-specific memory configuration in terms of processing time and energy consumption. © 2017, Springer-Verlag GmbH Germany.

关键词： Memory architecture

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Reliably locking system v shared memory for user level communication in linux

Reliably locking system v shared memory for user level commu...

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2001 IEEE International Conference on Cluster Computing, CLUSTER 2001

作者： Seifert, Friedrich Rehm, Wolfgang Chemnitz University of Technology Department of Computer Science Chair of Computer Architecture Strabe der Nationen 62 Chemnitz09111 Germany

ISBN: (纸本)0769511163

A major trend in recent cluster communication systems is to circumvent the operating system during the actual data transfers. That, on the one hand, reduces latency since there is no user-kernel transition needed and, on the other hand, increases bandwidth by avoiding additional intermediate copies. The data transfer is handled completely by the networking hardware and its DMA engine. For example, the Virtual Interface processes can access networking hardware directly in a protected manner. One of its characteristics is that it requires that all memory used for communication be locked down into physical memory. The same requirement holds true for the Infiniband ensures reliable locking of regular, i.e. private, virtual memory without altering the kernel. In this paper we present an extended solution that can handle System V shared memory as well. © 2001 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： Linux

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An annotation tool for enhancing the user interface generation process for services

An annotation tool for enhancing the user interface generati...

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KpbiMuKo 2009 CriMiCo - 2009 19th International Crimean Conference Microwave and Telecommunication Technology

作者： Izquierdo, Paoli Janeiro, Jordan Hübsch, Gerald Springer, Thomas Schill, Alexander Department of Computer Science Institute of System Architecture Chair of Computer Networks Dresden Technical University Dresden Sachsen 01187 Germany

ISBN: (纸本)9789663352497

The user interface generation process is still a complex issue. The manual creation process is time consuming and complex because it requires the combination of the application developer work and the user interface designer work. Therefore, many approaches investigate the automatic user interface generation. However, currently such approaches are not able to take usability aspects into account, due to the lack of information for such a process. Thus, we propose a tool which intends to ease and enhance the automatic user interface generation process for services by introducing service annotations that are attached to services and provide additional information for the process of automatic user interface generation. © 2009: CriMiCo'2009 Organizing Committee.

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PERFORMANCE EVALUATION PRINCIPLES FOR VECTOR AND MULTIPROCESSOR SYSTEMS

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PARALLEL COMPUTING 1988年第3期7卷 425-438页

作者： HERZOG, U Institute for Mathematical Machines and Data Processing Friedrich-Alexander-University Erlangen-Nürnberg Chair for Computer Architecture and Performance Evaluation D-8520 Erlangen Fed. Rep. Germany

Skilful computer system measurement, modelling and performance evaluation techniques are needed for supercomputer architectures. They allow to accurately determine characteristics performance values, to find potential hardware- and software-bottleneck; they also help to efficiently distribute and schedule user tasks. This paper is an extended version of a tutorial contribution at the IEEE CompEuro 87 and surveys fundamental performance issues and their solution for supercomputer architectures.

关键词： modelling memory interference modelling synchronization problems monitoring techniques multiprocessor systems performance measures Vector computer

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