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检索条件"机构=Chair for Chip Design for Embedded Computing"

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Experimental Radiation Effect Characterization for Microelectronics

Experimental Radiation Effect Characterization for Microelec...

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2025 Pan Pacific Strategic Electronics Symposium, Pan Pacific 2025

作者： Trumann, Eike Thieu, Gia Bao Vaya, Guillermo Pava Weide-Zaage, Kirsten Technische Universität Braunschweig Chair for Chip Design for Embedded Computing Braunschweig Germany Leibniz Universität Hannover RESRI Group Hannover Germany

ISBN: (纸本)9781944543358

In the process of developing high-reliability microelectronics, experimental radiation testing plays a vital role in assuring the durability and correct functionality of the device. As three major classes of radiation effects affect components, different radiation qualification tests must be combined to give comprehensive radiation hardness assurance. This work provides an overview of radiation testing standards, radiation sources, and important considerations for radiation testing. © 2025 SMTA.

关键词： Radiation effects

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Experimental Radiation Effect Characterization for Microelectronics

Experimental Radiation Effect Characterization for Microelec...

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Pan Pacific Microelectronics Symposium (Pan Pacific)

作者： Eike Trumann Gia Bao Thieu Guillermo Pavá Vayá Kirsten Weide-Zaage Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Braunschweig Germany RESRI Group Institute of Microelectronic Systems (IMS) Leibniz Universität Hannover Hannover Germany

ISBN: (数字)9781944543358

ISBN: (纸本)9798331511982

关键词： Radiation effects Electronic components Microelectronics Reliability Standards Testing Qualifications Formal verification

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PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations 23rd

PATARA: Extension of a Verification Framework for RISC-V Ins...

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23rd International Conference on embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2023

作者： Gesper, Sven Stuckmann, Fabian Wöbbekind, Lucy Payá-Vayá, Guillermo Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Braunschweig Germany

ISBN: (纸本)9783031460760

Compliance testing is mandatory when implementing the hardware architecture of a specific RISC-V instruction set. An official compliance test suite with handwritten test cases can be helpful for this verification task. However, a high-quality test suite requires significant manual effort and cannot easily adapt to specific processor hardware architecture organization implementation aspects such as single-cycle, multi-cycle, or pipeline (with a different number of pipeline stages) configurations. This issue can be resolved by using an automatic test generation framework. However, these frameworks require the execution of a golden reference model for functional verification, which increases the verification time and introduces additional error possibilities. This paper extends the PATARA framework, based on the REVERSI approach, to generate randomized, self-testing test cases for any RISC-V hardware implementation. The REVERSI method takes profit of the instruction set to reverse the functionality of one instruction with other ones, verifying the functionality within the same test program and without requiring a golden reference model (e.g., simulator). The PATARA framework is extended to generate tests covering all possible hardware architecture implementation hazards and cache misses by taking into account different processor architecture parameters. In order to validate the methodology, a case study is used to verify a 6 pipeline-stages RV32IM hardware architecture implementation, reaching up to 100 % condition coverage with the REVERSI self-testing approach against 78.94% coverage achieved by the official handwritten compliance test framework. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Software testing

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Simulation of Different SRAM Cells under Neutron Radiation with GEANT4 25

Simulation of Different SRAM Cells under Neutron Radiation w...

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25th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2024

作者： Weide-Zaage, Kirsten Mandala, Satria-Jaya Trumann, Eike Paya-Vaya, Guillermo Wolff, Dorian Von Bausen, Andre Muller, Alexander Leibniz Universität Hannover RESRI Group Hannover Germany Technische Universität Braunschweig Chair for Chip Design for Embedded Computing Braunschweig Germany Munster Germany

ISBN: (纸本)9798350393637

The simulation tool GEANT4 is used for the simulation of particle interaction under radiation exposure. In this investigation the tool is used to calculate the interaction of neutrons in the SRAM cells in the active means transistor region of the cells. The goal is to determine the sensitivity to bit flips. The determination of the linear energy transfer (LET) depending on the count of transistors and cell size was investigated. The investigated SRAM-cells were fabricated in a 180nm node. The neutron radiation energy which may lead to a single event upset (SEU) was determined. The simulation was carried out with different particle energies of 1.6MeV, 2.45MeV, 6MeV and 14MeV. Threshold energies are necessary to initiate a bit flip. With the help of the simulation, the energy transfer into the active region can be determined. As a result, the adaptation of measurement (radiation time and dose) can be done. © 2024 IEEE.

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N2V2PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture 13

N2V2PRO: Neural Network Mapping Framework for a Custom Vecto...

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13th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2023

作者： Gesper, Sven Thieu, Gia Bao Kohler, Daniel Kock, Markus Berthold, Tim Renke, Oliver Blume, Holger Paya-Vaya, Guillermo Technische Universität Chair for Chip Design for Embedded Computing Braunschweig Germany Robert Bosch GmbH Germany Dream Chip Technologies GmbH Germany Institute of Microelectronic Systems Leibniz Universität Hannover Germany

ISBN: (纸本)9798350324150

Convolutional neural networks (CNNs) have been demonstrated to be a successful approach in the field of artificial intelligence (AI). Deploying CNNs on embedded devices at a large scale would contribute significantly to the advancement and practical implementation of AI in various industries. However, the complexity of CNNs in terms of memory and operation requirements poses challenges in terms of computing performance, memory bandwidth, and flexibility of the executing hardware. This paper introduces a framework that addresses these issues through model quantization and hardware acceleration on a scalable vertical vector processor architecture. Firstly, the framework includes a method for layer fusion, which is designed to optimize the hardware utilization. Secondly, data storage is optimized to enhance memory efficiency. Lastly, CNNs are mapped onto the vertical vector processing concept of the hardware accelerator. The effectiveness of the proposed framework is evaluated by analyzing the accelerator efficiency based on a field-programmable gate array (FPGA). The results demonstrate that the framework offers flexibility, configurability, and efficient mapping for typical CNN implementations. The framework achieves up to 84% of the peak performance of the vector processor for the VGG net. © 2023 IEEE.

关键词： Mapping

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A Graph Neural Network Approach to Improve List Scheduling Heuristics Under Register-Pressure

A Graph Neural Network Approach to Improve List Scheduling H...

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International Conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Fabian Stuckmann Guillermo Payá–Vayá Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Germany

ISBN: (数字)9798350385427

ISBN: (纸本)9798350385434

Code generation (for VLIW processor architectures) consists of instruction scheduling and register allocation. For instruction scheduling, a list scheduling heuristic is often used. However, list scheduling heuristics do not consider registerfile constraints, such as register-pressure. Thus, if the number of alive variables (i.e., virtual registers) is higher than that of available physical registers (i.e., register-pressure), register spilling instructions (i.e., store and load instructions) must be introduced to free up physical registers during register allocation. This leads to a reduction of the code compaction, decreasing the performance. This paper introduces a Graph Neural Network (GNN), that prevents register spilling by reducing the registerpressure during the instruction scheduling, and the required Reinforcement Learning (RL) environment for training. Across a test-suite including 118 random assembly programs, where 22 (18.6%) cannot schedule using list scheduling heuristic without using register spilling to alleviate register-pressure, the proposed GNN approach is able to schedule 117 programs, reducing the number of not schedulable programs to 0.8%. Moreover, the proposed GNN scheduler is able to optimally schedule up to 115 (97.5%) of the assembly programs, compared to an evolutionarybased combined instruction scheduling and register allocation approach.

关键词： Training Schedules Codes Processor scheduling Reinforcement learning Graph neural networks Registers

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A lightweight-system-level power and area estimation methodology for application specific instruction set processors

A lightweight-system-level power and area estimation methodo...

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International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

作者： Syed Abbas Ali Shah Jan Wagner Thomas Schuster Mladen Berekovic Technische Universitat Braunschweig Braunschweig Niedersachsen DE Chair for Chip Design for Embedded Computing TU Braunschweig Germany

Detailed power estimation is a tedious and time consuming task in modern ASIP design. To facilitate this process, we present faster and fully automated estimation models for use at system level. In the first step of our approach, we calculate normalized values for all the basic design components of the processor that are related to power and area (e.g. memories, register files, function units, etc). These normalized values are estimated based on processors with different configurations (e.g., different memory sizes) and then stored in a database. Later, in the second step, this information is used to estimate the power of new derived architectures. To that end, we combine the previously calculated normalized power data with the component configurations and switching information from system-level simulation. The approach is demonstrated on the example of an Intel ASIP design flow (Silicon Hive). We report power and area estimates for four different ASIP designs. The mean error of the area prediction is 10%, while the mean error in power prediction is 15%.

关键词： Estimation Computer architecture Program processors Computational modeling Registers Silicon System-on-chip

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A 505nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs

A 505nW Programmable NanoController in 22 nm FDSOI-CMOS for ...

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Norchip

作者： Moritz Weißbrich Alexander Meyer Adilet Dossanov Vadim Issakov Guillermo Payá-Vayá Chair for Chip Design for Embedded Computing TU Braunschweig Braunschweig Germany Institute for CMOS Design TU Braunschweig Braunschweig Germany

ISBN: (数字)9798331517663

ISBN: (纸本)9798331517670

The realization of autonomous, wearable, and implantable Systems-on-chip (SoC) for health monitoring applications poses several challenges, such as achieving ultra-low size, cost, and power consumption, yet offering sufficient flexibility to re-program and adapt the autonomously operating SoC during the course of treatment. Commonly, programmability is not considered for ultra-low-power biomedical SoCs, since a dedicated finite state machine fixes the operation sequence. This work proposes a combination of a programmable NanoController with a SAR ADC, for potential use in ultra-low-power wearable or implantable biomedical SoCs, and integrates it as a prototype chip in a 22nm FDSOI-CMOS technology. The proposed NanoController achieves an extremely low power consumption of 505nW when programmed for 10-bit SAR ADC control and a sample rate of 100 kSamples/s. This result shows that energy efficiency and programmability during operation are not mutually exclusive for smart ultra-low-power biomedical platform chips. Based on the results of this prototype chip, a fully-integrated glucose sensor chip has been designed and submitted for fabrication, which will be evaluated in future work.

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Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms

Safe Virtual Interrupts Leveraging Distributed Shared Resour...

引用

Pacific Rim International Symposium on Dependable computing

作者： Boris Motruk Jonas Diemer Philip Axer Rainer Buchty Mladen Berekovic Chair for Chip Design for Embedded Computing Institute of Computer and Network Engineering Technische Universität Braunschweig Germany

Modern many-core platforms offer sufficient redundant resources for increasing availability and fault-tolerance of multiple applications, also of different criticality (mixed-criticality). A suitable platform must allow remapping applications and replacing peripherals dynamically. Mapping to distributed resources but also communication among resources ideally is transparent and flexible to allow changes at run time. Communication additionally has to be predictable, especially for safety-critical applications, and can be efficiently implemented by the use of interrupt requests. This paper presents a scalable interrupt translation mechanism supporting flexible and transparent communication among resources. Our contribution is of particular benefit for legacy applications but also eases development of new applications. A fast and predictable monitoring and control mechanism enforces specified behavior of applications and peripherals communicating with critical applications at run time. This significantly reduces integration effort for mixed-critical applications on a shared platform, and thus makes many-core platforms more attractive for embedded and safety-critical systems.

关键词： Tiles Monitoring Network interfaces Program processors Control systems Safety

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Efficient Barrier Synchronization for OpenMP-Like Parallelism on the Intel SCC

Efficient Barrier Synchronization for OpenMP-Like Parallelis...

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Hayder Al-Khalissi Rainer Bucty Mladen Berekovic Chair of Chip-Design for Embedded Computing TU Braunschweig Braunschweig Germany Technische Universitat Braunschweig Braunschweig Niedersachsen DE

The continuous increase of the number of processing cores on die poses a new set of challenges to HPC applications programming including how to model, write, and verify software that has to use the full power of NoC-based manycore processors. Therefore, to simplify program development for the Single-chip Cloud Computer (SCC), it is desirable to have high-level, shared memory-based parallel programming abstractions (e.g., an OpenMP-like programming model). One of the key components of any similar programming model are barrier synchronization primitives, coordinating the work of parallel threads. To allow high-level barrier constructs to deliver good performance, we need an efficient implementation of the underlying synchronization algorithm. In this paper, we propose effective barrier synchronization implementations for shared-memory programming on non-cache-coherent cluster-on-chip represented by the Intel SCC. In particular, we present an extensive evaluation of the overhead associated with integrating barrier algorithms required for OpenMP runtime libraries on such a machine, validating several implementation variants that efficiently exploit the network topology and leveraging SCC-specific hardware. We provide a detailed evaluation of the performance achieved by different approaches by using micro-benchmarks.

关键词： Message systems Synchronization Table lookup Delays Instruction sets Programming Radiation detectors

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