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Euromicro Conference on Parallel, Distributed and Network-Based Processing

作者： Patrick Siegl Rainer Buchty Mladen Berekovic Chair for Chip Design for Embedded Computing (C3E) Technische Universität Carolo-Wilhelminazu Braunschweig

Heterogeneous system architectures are becoming more and more of a commodity in the scientific community. While it remains challenging to fully exploit such architectures, the benefits in performance and hybrid speed-up, by using a host processor and accelerators in parallel in a non-monolithic matter, are significant. Hereby, the energy efficiency is becoming an increasingly critical challenge for future high-performance computing (HPC) systems, which do want to exceed the Exascale barrier with several competing architecture concepts ranging from high-performance CPUs, combined with GPUs acting as floating-point accelerators, to computationally weak CPUs, paired with dedicated and highly-perform ant FPGA-based accelerators. In this paper, we realize and evaluate a hybrid computing approach based on a two-dimensional seismic streaming algorithm with several heterogeneous system architectures, including conventional HPC approaches based on powerful CPUs and GPUs. Furthermore, we elaborate the effort on an embedded system platform claiming to be a "mini supercomputer" [1]. Several CPU and accelerator combinations are utilized in a manual work-sharing manner with the aim of achieving significant performance speed-ups and a detailed energy-efficiency study. Based on roofline models and experimental evaluations, the paper provides an insight into the fact that hybrid computing is mostly unconditionally beneficial for balanced systems regarding the performance as well as the energy efficiency, aiding the programmer in the decision whether or not costly, manually tuned, homogeneous implementations are worthwhile.

关键词： Graphics processing units Computer architecture Partitioning algorithms Benchmark testing Instruction sets Computational modeling Performance evaluation

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IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality

IDAMC: A Many-Core Platform with Run-Time Monitoring for Mix...

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IEEE International Symposim on High Assurance Systems Engineering

作者： Boris Motruk Jonas Diemer Rainer Buchty Rolf Ernst Mladen Berekovic Institute of Computer and Network Engineering Technische Universitäat Braunschweig Germany Chair of Chip Design for Embedded Computing Technische Universitäat Braunschweig Germany

On a multi- or many-core platform that runs applications of different safety criticality (mixed-criticality), all applications have to be certified to the highest level of criticality, unless they are sufficiently isolated. Isolation enables individual certification of applications and cost-efficient re-certification of single applications after an update. We introduce a parameterizable and synthesizable many-core platform with a fast and scalable monitoring and control mechanism that supports safe sharing of resources. Our contribution is a step towards exploiting the benefits of multi- and many-core platforms for mixed-critical applications.

关键词： Tiles Monitoring Safety Control systems Nickel Network interfaces Delay

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A 4 W Low-Power Audio Processor System for Real-Time Jaw Movements Recognition in Grazing Cattle

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Journal of Signal Processing Systems 2022年第4期95卷 407-424页

作者： Martinez-Rau, Luciano S. Weißbrich, Moritz Payá-Vayá, Guillermo Research Institute for Signals Systems and Computational Intelligence sinc(i) FICH-UNL/CONICET Santa Fe Argentina Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Braunschweig Germany

Precision livestock farming consists of technological tools and techniques to improve livestock management. Proper detection and classification of jaw movement (JM) events are indispensable for the estimation of dry matter intake, detection of health problems, and flag the onset of estrus, among other information. The analysis of acoustic signals is one of the most accepted ways to monitor the feeding behavior of free-grazing cattle. Different acoustic methods have been developed for recognizing JM-events in recent years. However, their operation is limited to off-line analysis on a personal computer. The lack of on-line acoustic monitoring systems is associated with the challenging operation requirements (low-power consumption, autonomy, portability, robustness and non-intrusive on the animal). In this paper, a fixed-point variant of the chew-bite energy-based algorithm is presented. This algorithm is implemented on a new low-power audio processor system for real-time recognition of JM-events. The system includes a Nanocontroller processor, which is always-on and detects JM-events; and a second transport-triggered architecture (TTA) based processor, which is mainly in power-down and classifies JM-events. The results demonstrate that the proposed fixed-point JM-events recognizer achieves a recognition rate of 91.4% and 90.2% in noiseless and noisy conditions, respectively. The recognition rate increases by 6.1% regarding a previous reference on-line system. Moreover, the proposed audio processor system chip consumes 4 μW on average, i.e., only 2.3% of the power of an always-on TTA-based processor system for the same audio sequence. An exemplary implementation of the proposed system in a 65 nm low-leakage CMOS technology is given.

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Multi-Level Prototyping of a Vertical Vector AI Processing System

Multi-Level Prototyping of a Vertical Vector AI Processing S...

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International Conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Frederik Kautz Sven Gesper Gia Bao Thieu Hans-Martin Bluethgen Holger Blume Guillermo Payá-Vayá Institute of Microelectronic Systems Leibniz University Hannover Germany Cadence Design Systems GmbH Munich Germany Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Germany

ISBN: (数字)9798350349634

ISBN: (纸本)9798350349641

Modern embedded systems must be designed carefully to cope with the complexity and real-time requirements of modern AI (Artificial Intelligence) driven automotive applications, such as Advanced Driver-Assistance Systems (ADAS). Despite increasing complexity, the time to market is decreasing. In this work, a SystemC-based Virtual Prototype of a neural network processing platform is exploited to bypass the limitations of standalone instruction set simulators (ISS) and FPGA prototyping. The processing platform under test is based on a novel massive parallel vector processor architecture coupled with a RISC- V control core that runs widely used convolutional neural networks (CNNs) for object detection. The paper discusses the variations and appropriateness of the three prototyping methods outlined, demonstrating how the Virtual Prototype can address the aforementioned constraints, resulting in a 2.07x increase in accuracy, 16x greater configurations, and more profound insights into the system compared to standalone and FPGA prototyping.

关键词： Accuracy Neural networks Prototypes Time to market Vectors Space exploration Complexity theory

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A Silicon-Proof Controller System for Flexible Ultra-Low-Power Energy Harvesting Platforms

A Silicon-Proof Controller System for Flexible Ultra-Low-Pow...

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International Conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Moritz Weiß brich Holger Blume Guillermo Payá -Vayá Chair for Chip Design for Embedded Computing Technische Universit&#x00E4 t Braunschweig Braunschweig Germany Institute of Microelectronic Systems Leibniz Universit&#x00E4 t Hannover Hannover Germany

ISBN: (数字)9781665467179

ISBN: (纸本)9781665467186

In this paper, a heterogeneous controller system and its first-silicon ASIC implementation are presented, where the use of a programmable NanoController next to a general-purpose microcontroller enables more efficient and flexible power management strategies than typical timer-based, periodical power-up of a single microcontroller in state-of-the-art IoT devices. The NanoController features a compact, control-oriented 4-bit ISA, which is used to continuously pre-process data in order to decide when to power-up the microcontroller required for infrequent complex processing, e.g., encrypted wireless communication. Despite its programmability, the required silicon area and power consumption are very small and enable the use in the always-on domain of SoCs for energy harvesting platforms, instead of much simpler and constrained timer circuits. The first-silicon ASIC implementation of such a controller system using a 65nm UMC low-leakage process is presented and evaluated for a real home automation application intended to operate on harvested energy, i.e., electronic door lock, reducing the average power consumption of reference microcontrollers by up to 20x.

关键词： Power demand Power measurement Microcontrollers Power system management Process control Logic gates Control systems

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N2V2PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture

N2V2PRO: Neural Network Mapping Framework for a Custom Vecto...

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IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin)

作者： Sven Gesper Gia Bao Thieu Daniel Köhler Markus Kock Tim Berthold Oliver Renke Holger Blume Guillermo Payá-Vayá Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Germany Robert Bosch GmbH Germany Dream Chip Technologies GmbH Germany Institute of Microelectronic Systems Leibniz Universität Hannover Germany

Convolutional neural networks (CNNs) have been demonstrated to be a successful approach in the field of artificial intelligence (AI). Deploying CNNs on embedded devices at a large scale would contribute significantly to the advancement and practical implementation of AI in various industries. However, the complexity of CNNs in terms of memory and operation requirements poses challenges in terms of computing performance, memory bandwidth, and flexibility of the executing hardware. This paper introduces a framework that addresses these issues through model quantization and hardware acceleration on a scalable vertical vector processor architecture. Firstly, the framework includes a method for layer fusion, which is designed to optimize the hardware utilization. Secondly, data storage is optimized to enhance memory efficiency. Lastly, CNNs are mapped onto the vertical vector processing concept of the hardware accelerator. The effectiveness of the proposed framework is evaluated by analyzing the accelerator efficiency based on a field-programmable gate array (FPGA). The results demonstrate that the framework offers flexibility, configurability, and efficient mapping for typical CNN implementations. The framework achieves up to 84% of the peak performance of the vector processor for the VGG net.

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Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency

Exploiting Subword Permutations to Maximize CNN Compute Perf...

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International Conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Michael Beyer Sven Gesper Andre Guntoro Guillermo Payá-Vayá Holger Blume Bosch Corporate Research Robert Bosch GmbH Renningen Germany Institute of Microelectronic Systems Leibniz University Hannover Germany Chair for Chip Design for Embedded Computing Technical University Braunschweig Germany

Neural networks (NNs) are quantized to decrease their computational demands and reduce their memory foot-print. However, specialized hardware is required that supports computations with low bit widths to take advantage of such optimizations. In this work, we propose permutations on subword level that build on top of multi-bit-width multiply-accumulate operations to effectively support low bit width computations of quantized NNs. By applying this technique, we extend the data reuse and further improve compute performance for convolution operations compared to simple vectorization using SIMD (single-instruction-multiple-data). We perform a design space exploration using a cycle accurate simulation with MobileNet and VGG16 on a vector-based processor. The results show a speedup of up to $3.7\times$ and a reduction of up to $1.9\times$ for required data transfers. Additionally, the control overhead for orchestrating the computation is decreased by up to $3.9\times$ .

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Architecture of computing Systems – ARCS 2018 1

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丛书名： Lecture Notes in Computer Science

1000年

作者： Mladen Berekovic Rainer Buchty Heiko Hamann Dirk Koch Thilo Pionteck

This book constitutes the proceedings of the 31st International Conference on Architecture of computing Systems, ARCS 2018, held in Braunschweig, Germany, in April 2018.

ISBN: (数字)9783319776101

ISBN: (纸本)9783319776095

This book constitutes the proceedings of the 31st International Conference on Architecture of computing Systems, ARCS 2018, held in Braunschweig, Germany, in April 2018.

关键词： Computer Communication Networks Logic design Operating Systems Processor Architectures Computer System Implementation Input/Output and Data Communications

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ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving

ZuSE Ki-Avf: Application-Specific AI Processor for Intellige...

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design, Automation and Test in Europe Conference and Exhibition

作者： Gia Bao Thieu Sven Gesper Guillermo Payá-Vayá Christoph Riggers Oliver Renke Till Fiedler Jakob Marten Tobias Stuckenberg Holger Blume Christian Weis Lukas Steiner Chirag Sudarshan Norbert Wehn Lennart M. Reimann Rainer Leupers Michael Beyer Daniel Köhler Alisa Jauch Jan Micha Borrmann Setareh Jaberansari Tim Berthold Meinolf Blawat Markus Kock Gregor Schewior Jens Benndorf Frederik Kautz Hans-Martin Bluethgen Christian Sauer Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Germany Institute of Microelectronic Systems Leibniz Universität Hannover Germany Microelectronic Systems Design Research Group Technische Universität Kaiserslautern Germany Institute for Communication Technologies and Embedded Systems RWTH Aachen University Germany Robert Bosch GmbH Germany Dream chip Technologies GmbH Germany Cadence Design Systems Germany

Modern and future AI-based automotive applications, such as autonomous driving, require the efficient real-time processing of huge amounts of data from different sensors, like camera, radar, and LiDAR. In the ZuSE-KI-AVF project, multiple university, and industry partners collaborate to develop a novel massive parallel processor architecture, based on a cus-tomized RISC-V host processor, and an efficient high-performance vertical vector coprocessor. In addition, a software development framework is also provided to efficiently program AI-based sensor processing applications. The proposed processor system was verified and evaluated on a state-of-the-art UltraScale+ FPGA board, reaching a processing performance of up to 126.9 FPS, while executing the YOLO-LITE CNN on 224x224 input images. Further optimizations of the FPGA design and the realization of the processor system on a 22nm FDSOI CMOS technology are planned.

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DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor

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ACM Transactions on Architecture and Code Optimization 1000年

作者： Gia Bao Thieu Sven Gesper Guillermo Payá-Vayá Chair for Chip Design for Embedded Computing TU Braunschweig Braunschweig Germany

State-of-the-art applications, such as convolutional neural networks, demand specialized hardware accelerators that address performance and efficiency constraints. An efficient memory hierarchy is mandatory for such hardware systems. While the memory architectures of general-purpose processors (e.g., CPU or GPUs) are based on cache systems, dedicated accelerators have mostly adopted the DMA (Direct Memory Access) concept due to the application field of image processing. DMA features like 2D data transfers or data padding can optimize the memory accesses of image processing. However, DMA lacks the capability to exploit temporal and spatial data reuse, a feature common in cache systems, particularly when multiple DMAs operate in parallel. This paper proposes a novel Direct Cached Memory Access (DCMA) architecture, combining both DMA and cache methodologies and their respective advantages. Optimized for image-based AI algorithms, the DCMA architecture facilitates enhanced memory access by integrating multiple, parallel DMA ports with caching capabilities. This design allows for efficient data reuse and parallel memory access. Optimal parameters for the DCMA are determined through a comprehensive design space exploration. The DCMA is evaluated on a state-of-the-art Xilinx UltraScale+ FPGA board coupled with a massive-parallel vertical vector co-processor, called V2PRO. The results show the mitigation of the vector processor’s memory bottleneck. By using the proposed DCMA, speedups of up to x17 for the ResNet-50 CNN can be achieved.

关键词： Cache DMA Hybrid DMA-Cache Vertical Vector Processor Memory Hierarchy Machine Learning

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