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2023 IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2023

作者： Schlemon, Maron Schulz, Martin Scheiber, Rolf Jasger, Marc Oliva, Joel Amao Germany Technical University of Munich Computer Architecture and Parallel Systems Germany

Synthetic Aperture Radar (SAR) enables the generation of realistic and high-resolution 2D or 3D representations of landscapes. Typically, radar instruments are deployed in specially equipped, low-flying aircraft that capture a significant amount of raw data, necessitating image reconstruction processing. However, the aircraft's limited onboard processing capabilities (power, size, weight, cooling, and communication bandwidth to ground stations) and the need to generate multiple SAR products, such as slant-range and geo-coded images during a single flight, require efficient onboard processing and transmission to the ground station. This paper outlines the processing architecture of the digital beamforming SAR (DBFSAR) employed by the German Aerospace Center (DLR) and the specific measures implemented to enable onboard processing. We elucidate the essential software optimizations and their integration into the SAR onboard routines, facilitating (near) real-time capability under certain conditions. Furthermore, we share the insights gained from our work and discuss their applicability to other processing scenarios with limited resource availability. © 2023 IEEE.

关键词： Synthetic aperture radar

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VersaSlot: Efficient Fine-grained FPGA Sharing with *** Slots and Live Migration in FPGA Cluster

arXiv

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arXiv 2025年

作者： Gu, Jianfeng Wang, Hao Guo, Xiaorang Schulz, Martin Gerndt, Michael Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

As FPGAs gain popularity for on-demand application acceleration in data center computing, dynamic partial reconfiguration (DPR) has become an effective fine-grained sharing technique for FPGA multiplexing. However, current FPGA sharing encounters partial reconfiguration contention and task execution blocking problems introduced by the DPR, which significantly degrade application performance. In this paper, we propose VersaSlot, an efficient spatio-temporal FPGA sharing system with novel *** slot architecture that can effectively resolve the contention and task blocking while improving resource utilization. For the heterogeneous *** architecture, we introduce an efficient slot allocation and scheduling algorithm, along with a seamless cross-board switching and live migration mechanism, to maximize FPGA multiplexing across the cluster. We evaluate the VersaSlot system on an FPGA cluster composed of the latest Xilinx UltraScale+ FPGAs (ZCU216) and compare its performance against four existing scheduling algorithms. The results demonstrate that VersaSlot achieves up to 13.66x lower average response time than the traditional temporal FPGA multiplexing, and up to 2.19x average response time improvement over the state-of-the-art spatio-temporal sharing systems. Furthermore, VersaSlot enhances the LUT and FF resource utilization by 35% and 29% on average, respectively. Copyright © 2025, The Authors. All rights reserved.

关键词： Scheduling algorithms

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Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing

Design of an FPGA-Based Neutral Atom Rearrangement Accelerat...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Xiaorang Guo Jonas Winklmann Dirk Stober Amr Elsharkawy Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Neutral atoms have emerged as a promising technology for implementing quantum computers due to their scalability and long coherence times. However, the execution frequency of neutral atom quantum computers is constrained by image processing procedures, particularly the assembly of defect-free atom arrays, which is a crucial step in preparing qubits (atoms) for execution. To optimize this assembly process, we propose a novel quadrant-based rearrangement algorithm that employs a divide-and-conquer strategy and also enables the simultaneous movement of multiple atoms, even across different columns and rows. We implement the algorithm on Field Programmable Gate Arrays (FPGAs) to handle each quadrant independently (hardware-level optimization) while maximizing parallelization. To the best of our knowledge, this is the first hardware acceleration work for atom rearrangement, and it significantly reduces the processing time. This achievement also contributes to the ongoing efforts of tightly integrating quantum accelerators into High-Performance Computing (HPC) systems. Tested on a Zynq RFSoC FPGA at 250 MHz, our hardware implementation is able to complete the rearrangement process of a 30 × 30 compact target array, derived from a 50 × 50 initial loaded array, in approximately 1.0 μs. Compared to a comparable CPU implementation and to state-of-the-art FPGA work, we achieved about 54 x and 300 x speedups in the rearrangement analysis time, respectively. Additionally, the FPGA-based acceleration demonstrates good scalability, allowing for seamless adaptation to varying sizes of the atom array, which makes this algorithm a promising solution for large-scale quantum systems.

关键词： computers Schedules Quantum system Quantum computing Scalability Qubit Atoms Central Processing Unit Field programmable gate arrays Assembly

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Integration of Quantum Accelerators into HPC: Toward a Unified Quantum Platform

arXiv

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arXiv 2024年

作者： Elsharkawy, Amr Guo, Xiaorang Schulz, Martin Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale superlinearly with number of qubits, which is critical to support scalability efforts in QC hardware. Copyright © 2024, The Authors. All rights reserved.

关键词： Trapped ions

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Integration of Quantum Accelerators into HPC: Toward a Unified Quantum Platform

Integration of Quantum Accelerators into HPC: Toward a Unifi...

引用

Quantum Computing and Engineering (QCE), IEEE International Conference on

作者： Amr Elsharkawy Xiaorang Guo Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

ISBN: (数字)9798331541378

ISBN: (纸本)9798331541385

To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale super-linearly with number of qubits, which is critical to support scalability efforts in OC hardware.

关键词： Runtime library Scalability High performance computing Qubit Process control Atoms Hardware Software Performance analysis Logic

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A Scalable and Cross-Technology Quantum Control Processor

A Scalable and Cross-Technology Quantum Control Processor

引用

International Conference on Field Programmable Logic and Applications

作者： Xiaorang Guo Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany

Quantum control processors (QCPs) bridge the gap between the quantum software and the hardware backend to construct full-stack quantum computers. In this study, the quantum backend interface is responsible for generating pulses to control qubits, where commercial waveform generators or specific converters are typically needed. A radio frequency system-on-chip (RFSoC)-based QCP supports a direct control pulse synthesis without additional components. Therefore, in this work, we propose an RFSoC-based QCP that integrates the processor and pulse generation logic onto a single board. With the help of the proposed instruction set and efficient microarchitecture implementation, the QCP offers large scalability for controllable qubits, while supporting different physical platforms.

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Leveraging Hybrid Classical-Quantum Methods for Efficient Load Rebalancing in HPC

Leveraging Hybrid Classical-Quantum Methods for Efficient Lo...

引用

2024 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC Workshops 2024

作者： Zawalska, Justyna Chung, Minh Rycerz, Katarzyna Schulz, Laura Schulz, Martin Kranzlmuller, Dieter AGH University of Krakow Institute of Computer Science Krakow Poland CYFRONET AGH Academic Computer Center Krakow Poland Garching bei München Germany Chair for Computer Architecture and Parallel Systems Germany MNM-Team Germany

ISBN: (纸本)9798350355543

Load imbalance is a challenge for parallel applications in High Performance Computing (HPC). It is caused by processes having different execution times or load values, leading to idle or wait times at synchronization points, where faster processes must wait for the slowest process to catch up. To mitigate this issue, applications can employ load balancing (LB) strategies, which migrate load between processes to even out load. This is often referred to as the Load Rebalancing Problem (LRP). While many approaches solving the LRP exist, they can only be heuristics and hence further optimization potential exists. In our work, we turn to a novel approach by using hybrid classical-quantum approaches and present two versions of the constrained quadratic model for solving the LRP;the two differ in how they balance the number of qubits required with the types of applied constraints. We compare the quantum-based methods with classical methods using heuristic algorithms Greedy, Karmarkar-Karp, and ProactLB. We evaluate our approaches using imbalance ratio and speedup as metrics, as well as the number of migrated tasks to indicate overhead caused by migrations. Our results show that the quantum-based methods outperform the classic methods. For example, we need only 1/4 of the number of migrated tasks in a realistic use case compared with classical methods, particularly Greedy and KK, to balance the load. © 2024 IEEE.

关键词： CQM HPC HPCQC integration Load Rebalancing Quantum Computing task migration

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Realistic Neutral Atom Image Simulation 4

Realistic Neutral Atom Image Simulation

引用

4th IEEE International Conference on Quantum Computing and Engineering, QCE 2023

作者： Winklmann, Jonas Tsevas, Dimitrios Schulz, Martin Computer Architecture and Parallel Systems Technical University of Munich Munich Germany Max Planck Institute of Quantum Optics Quantum Many-Body Systems Division Garching Germany

ISBN: (纸本)9798350343236

Neutral atom quantum computers require accurate single atom detection for the preparation and readout of their qubits. This is usually done using fluorescence imaging. The occupancy of an atom site in these images is often somewhat ambiguous due to the stochastic nature of the imaging process. Further, the lack of ground truth makes it difficult to rate the accuracy of reconstruction algorithms. We introduce a bottom-up simulator that is capable of generating sample images of neutral atom experiments from a description of the actual state in the simulated system. Possible use cases include the creation of exemplary images for demonstration purposes, fast training iterations for deconvolution algorithms, and generation of labeled data for machine-learning-based atom detection approaches. The implementation is available through our GitHub as a C library or wrapped Python package. We show the modeled effects and implementation of the simulations at different stages of the imaging process. Not all real-world phenomena can be reproduced perfectly. The main discrepancies are that the simulator allows for only one characterization of optical aberrations across the whole image, supports only discrete atom locations, and does not model all effects of complementary metal-oxide-semiconductor (CMOS) cameras perfectly. Nevertheless, our experiments show that the generated images closely match real-world pictures to the point that they are practically indistinguishable and can be used as labeled data for training the next generation of detection algorithms. © 2023 IEEE.

关键词： Atoms

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Towards the Munich Quantum Software Stack: Enabling Efficient Access and Tool Support for Quantum computers 4

Towards the Munich Quantum Software Stack: Enabling Efficien...

引用

4th IEEE International Conference on Quantum Computing and Engineering, QCE 2023

作者： Schulz, Martin Schulz, Laura Ruefenacht, Martin Wille, Robert Technical University of Munich Computer Architecture and Parallel Systems Munich Germany Leibniz Supercomputing Centre Qct Department Garching Germany Technical University of Munich Design Automation Munich Germany

ISBN: (纸本)9798350343236

As quantum computing systems mature and move from laboratories to production computing environments, corresponding software stacks are becoming key for their successful utilization. In particular, the expected use of quantum systems as HPC accelerators requires a deep integration with the existing and widely deployed HPC software stacks. Additionally, new requirements such as dynamic compilation and new challenges for tools and programming models must be considered. We tackle these challenges by developing the Munich Quantum Software Stack - a comprehensive initiative by the Munich Quantum Valley to offer a flexible, efficient, and user-oriented software environment. In this poster, we describe the core components and workflows, and how they will enable this transformation from quantum experiments to quantum accelerators. © 2023 IEEE.

关键词： Quantum optics

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Real-Time Capability of DLR’S Beamforming Synthetic Aperture Radar Processing architecture

Real-Time Capability of DLR’S Beamforming Synthetic Apertur...

引用

Acoustics, Speech, and Signal Processing Workshops (ICASSPW), IEEE International Conference on

作者： Maron Schlemon Martin Schulz Rolf Scheiber Marc Jäger Joel Amao Oliva German Aerospace Center (DLR) Microwaves and Radar Institute Germany Chair of Computer Architecture and Parallel Systems Technical University of Munich Germany

ISBN: (数字)9798350374513

ISBN: (纸本)9798350374520

Synthetic Aperture Radar (SAR) enables the generation of realistic and high-resolution 2D or 3D representations of landscapes. Typically, radar instruments are deployed in specially equipped, low-flying aircraft that capture a significant amount of raw data, necessitating image reconstruction processing. However, the aircraft’s limited onboard processing capabilities (power, size, weight, cooling, and communication bandwidth to ground stations) and the need to generate multiple SAR products, such as slant-range and geo-coded images during a single flight, require efficient onboard processing and transmission to the ground station. This paper outlines the processing architecture of the digital beamforming SAR (DBFSAR) employed by the German Aerospace Center (DLR) and the specific measures implemented to enable onboard processing. We elucidate the essential software optimizations and their integration into the SAR onboard routines, facilitating (near) real-time capability under certain conditions. Furthermore, we share the insights gained from our work and discuss their applicability to other processing scenarios with limited resource availability.

关键词： Three-dimensional displays Array signal processing Instruments computer architecture Radar imaging Real-time systems Software

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