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arXiv 2025年

作者： Gu, Jianfeng Wang, Hao Guo, Xiaorang Schulz, Martin Gerndt, Michael Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

As FPGAs gain popularity for on-demand application acceleration in data center computing, dynamic partial reconfiguration (DPR) has become an effective fine-grained sharing technique for FPGA multiplexing. However, current FPGA sharing encounters partial reconfiguration contention and task execution blocking problems introduced by the DPR, which significantly degrade application performance. In this paper, we propose VersaSlot, an efficient spatio-temporal FPGA sharing system with novel *** slot architecture that can effectively resolve the contention and task blocking while improving resource utilization. For the heterogeneous *** architecture, we introduce an efficient slot allocation and scheduling algorithm, along with a seamless cross-board switching and live migration mechanism, to maximize FPGA multiplexing across the cluster. We evaluate the VersaSlot system on an FPGA cluster composed of the latest Xilinx UltraScale+ FPGAs (ZCU216) and compare its performance against four existing scheduling algorithms. The results demonstrate that VersaSlot achieves up to 13.66x lower average response time than the traditional temporal FPGA multiplexing, and up to 2.19x average response time improvement over the state-of-the-art spatio-temporal sharing systems. Furthermore, VersaSlot enhances the LUT and FF resource utilization by 35% and 29% on average, respectively. Copyright © 2025, The Authors. All rights reserved.

关键词： Scheduling algorithms

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Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing

Design of an FPGA-Based Neutral Atom Rearrangement Accelerat...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Xiaorang Guo Jonas Winklmann Dirk Stober Amr Elsharkawy Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Neutral atoms have emerged as a promising technology for implementing quantum computers due to their scalability and long coherence times. However, the execution frequency of neutral atom quantum computers is constrained by image processing procedures, particularly the assembly of defect-free atom arrays, which is a crucial step in preparing qubits (atoms) for execution. To optimize this assembly process, we propose a novel quadrant-based rearrangement algorithm that employs a divide-and-conquer strategy and also enables the simultaneous movement of multiple atoms, even across different columns and rows. We implement the algorithm on Field Programmable Gate Arrays (FPGAs) to handle each quadrant independently (hardware-level optimization) while maximizing parallelization. To the best of our knowledge, this is the first hardware acceleration work for atom rearrangement, and it significantly reduces the processing time. This achievement also contributes to the ongoing efforts of tightly integrating quantum accelerators into High-Performance Computing (HPC) systems. Tested on a Zynq RFSoC FPGA at 250 MHz, our hardware implementation is able to complete the rearrangement process of a 30 × 30 compact target array, derived from a 50 × 50 initial loaded array, in approximately 1.0 μs. Compared to a comparable CPU implementation and to state-of-the-art FPGA work, we achieved about 54 x and 300 x speedups in the rearrangement analysis time, respectively. Additionally, the FPGA-based acceleration demonstrates good scalability, allowing for seamless adaptation to varying sizes of the atom array, which makes this algorithm a promising solution for large-scale quantum systems.

关键词： computers Schedules Quantum system Quantum computing Scalability Qubit Atoms Central Processing Unit Field programmable gate arrays Assembly

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KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA

arXiv

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arXiv 2025年

作者： Guo, Xiaorang Bunarjyan, Tigran Liu, Dai Lienhard, Benjamin Schulz, Martin Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany Department of Chemistry Princeton University PrincetonNJ08544 United States Department of Electrical and Computer Engineering Princeton University PrincetonNJ08544 United States

Superconducting qubits are among the most promising candidates for building quantum information processors. Yet, they are often limited by slow and error-prone qubit readout—a critical factor in achieving high-fidelity operations. While current methods, including deep neural networks, enhance readout accuracy, they typically lack support for mid-circuit measurements essential for quantum error correction, and they usually rely on large, resource-intensive network models. This paper presents KLiNQ, a novel qubit readout architecture leveraging lightweight neural networks optimized via knowledge distillation. Our approach achieves around a 99% reduction in model size compared to the baseline while maintaining a qubit-state discrimination accuracy of 91%. KLiNQ facilitates rapid, independent qubit-state readouts that enable mid-circuit measurements by assigning a dedicated, compact neural network for each qubit. Implemented on the Xilinx UltraScale+ FPGA, our design can perform the discrimination within 32 ns. The results demonstrate that compressed neural networks can maintain high-fidelity independent readout while enabling efficient hardware implementation, advancing practical quantum computing. Copyright © 2025, The Authors. All rights reserved.

关键词： Field programmable gate arrays (FPGA)

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Telemetry for Quantum systems in HPC Centers

Telemetry for Quantum Systems in HPC Centers

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ISC High Performance 2025 Research Paper Proceedings (40th International Conference)

作者： Hossam Ahmed Burak Mete Helmut Heller Matthew Tovey Xiaolong Deng Asim Zulfiqar Muhammad Nufail Farooqi Mahmoud Abuzayed Martin Schulz Laura Schulz QCT Department Leibniz Supercomputing Centre of the Bavarian Academy of Science and Humanities (LRZ) Garching b. München Germany Chair for Computer Architecture and Parallel Systems (CAPS) Technical University of Munich (TUM) Garching b. München Germany

ISBN: (数字)9783982633619

Quantum systems have traditionally operated within highly controlled laboratory environments to minimize internal noise and maximize stability. However, when these systems are integrated into High Performance Computing (HPC) environments and setup for continuous operation, they encounter significantly higher levels of external noise and instability coupled with higher demands. This paper introduces a comprehensive framework to counter the challenges of maintaining the stability of operational quantum computers in such noisy HPC settings. We propose a novel system architecture that monitors and manages the environmental conditions of quantum computing systems using a broad set of sensors, enhancing their robustness and reliability. Our architecture is open and can be extended to other setups. It can serve as a blueprint for other sites as it spans quantum technologies and offers broad coverage. Ultimately, this data will be essential to facilitate advancements in machine learning to drive real-time error mitigation.

关键词： computers Quantum system Trapped ions Quantum computing Working environment noise systems architecture Machine learning Stability analysis Telemetry Monitoring

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VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

VRank: Enhancing Verilog Code Generation from Large Language...

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IEEE International Symposium on Quality Electronic Design

作者： Zhuorui Zhao Ruidi Qiu Ing-Chao Lin Grace Li Zhang Bing Li Ulf Schlichtmann Chair of Electronic Design Automation Technical University of Munich (TUM) Munich Germany Computer Architecture and IC Design National Cheng Kung University Hardware for Artificial Intelligence Group Technical University of Darmstadt Research Group of Digital Integrated Systems University of Siegen

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes, previous methods require either time-consuming manual inspection or generation of multiple Verilog codes, from which the one with the highest quality is selected with manually designed testbenches. To enhance the generation efficiency while maintaining the quality of the generated codes, we propose VRank, an automatic framework that generates Verilog codes with LLMs. In our framework, multiple code candidates are generated with LLMs by leveraging their probabilistic nature. Afterwards, we group Verilog code candidates into clusters based on identical outputs when tested against the same testbench, which is also generated by LLMs. Clusters are ranked based on the consistency they show on testbench. To determine the best candidate, Chain-of-Thought is further applied to select the best candidate from the top-ranked clusters. By systematically analyzing diverse outputs of generated codes, VRank reduces errors and enhances the overall quality of the generated Verilog code. Experimental results on the VerilogEval-Human benchmark demonstrate a significant 10.5% average increase in functional correctness (pass@1) across multiple LLMs, demonstrating VRank's effectiveness in improving the accuracy of automated hardware description language generation for complex design tasks.

关键词： Codes Accuracy Large language models Manuals Inspection Probabilistic logic Hardware Cognition Reliability Hardware design languages

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Leveraging Hybrid Classical-Quantum Methods for Efficient Load Rebalancing in HPC 24

Leveraging Hybrid Classical-Quantum Methods for Efficient Lo...

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Proceedings of the SC '24 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis

作者： Justyna Zawalska Minh Chung Katarzyna Rycerz Laura Schulz Martin Schulz Dieter Kranzlmüller AGH University of Krakow Institute of Computer Science Krakow Poland and Academic Computer Center CYFRONET AGH Krakow Poland Leibniz Supercomputing Centre (LRZ) Garching bei München Germany and MNM-Team Ludwig-Maximilians-Universität München (LMU) Germany Leibniz Supercomputing Centre (LRZ) Garching bei München Germany Leibniz Supercomputing Centre (LRZ) Garching bei München Germany and Chair for Computer Architecture and Parallel Systems Technical University of Munich (TUM) Germany

ISBN: (纸本)9798350355543

Load imbalance is a challenge for parallel applications in High Performance Computing (HPC). It is caused by processes having different execution times or load values, leading to idle or wait times at synchronization points, where faster processes must wait for the slowest process to catch up. To mitigate this issue, applications can employ load balancing (LB) strategies, which migrate load between processes to even out load. This is often referred to as the Load Rebalancing Problem (LRP). While many approaches solving the LRP exist, they can only be heuristics and hence further optimization potential exists. In our work, we turn to a novel approach by using hybrid classical-quantum approaches and present two versions of the constrained quadratic model for solving the LRP; the two differ in how they balance the number of qubits required with the types of applied constraints. We compare the quantum-based methods with classical methods using heuristic algorithms Greedy, Karmarkar--Karp, and ProactLB. We evaluate our approaches using imbalance ratio and speedup as metrics, as well as the number of migrated tasks to indicate overhead caused by migrations. Our results show that the quantum-based methods outperform the classic methods. For example, we need only 1/4 of the number of migrated tasks in a realistic use case compared with classical methods, particularly Greedy and KK, to balance the load.

关键词： CQM

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Real-Time Capability of Dlr's Beamforming Synthetic Aperture Radar Processing architecture

Real-Time Capability of Dlr's Beamforming Synthetic Aperture...

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2023 IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2023

作者： Schlemon, Maron Schulz, Martin Scheiber, Rolf Jasger, Marc Oliva, Joel Amao Germany Technical University of Munich Computer Architecture and Parallel Systems Germany

Synthetic Aperture Radar (SAR) enables the generation of realistic and high-resolution 2D or 3D representations of landscapes. Typically, radar instruments are deployed in specially equipped, low-flying aircraft that capture a significant amount of raw data, necessitating image reconstruction processing. However, the aircraft's limited onboard processing capabilities (power, size, weight, cooling, and communication bandwidth to ground stations) and the need to generate multiple SAR products, such as slant-range and geo-coded images during a single flight, require efficient onboard processing and transmission to the ground station. This paper outlines the processing architecture of the digital beamforming SAR (DBFSAR) employed by the German Aerospace Center (DLR) and the specific measures implemented to enable onboard processing. We elucidate the essential software optimizations and their integration into the SAR onboard routines, facilitating (near) real-time capability under certain conditions. Furthermore, we share the insights gained from our work and discuss their applicability to other processing scenarios with limited resource availability. © 2023 IEEE.

关键词： Synthetic aperture radar

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Time series mining at petascale performance 35th

Time series mining at petascale performance

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35th International Conference on High Performance Computing, ISC High Performance 2020

作者： Raoofy, Amir Karlstetter, Roman Yang, Dai Trinitis, Carsten Schulz, Martin Computer Architecture and Parallel Systems Technical University of Munich Garching Germany IfTA GmbH Puchheim Germany NVIDIA Munich Germany

ISBN: (纸本)9783030507428

The mining of time series data plays an important role in modern information retrieval and analysis systems. In particular, the identification of similarities within and across time series has garnered significant attention and effort over the last few years. For this task, the class of matrix profile algorithms, which create a generic structure that encodes correlations among records and dimensions—the matrix profile—is a promising approach, as it allows simplified post-processing and analysis steps by examining the resulting matrix profile structure. However, it is expensive to create a matrix profile: it requires significant computational power to evaluate the distance among all subsequence pairs in a time series, especially for very long and multi-dimensional time series with a large dimensionality. Existing approaches are limited in their scalability, as they do not target High Performance Computing systems, and—for most realistic problems—are suited only for datasets with a small dimensionality. In this paper, we introduce a novel MPI-based approach for the calculation of a matrix profile for multi-dimensional time series that pushes these limits. We evaluate the efficiency of our approach using an analytical performance model combined with experimental data. Finally, we demonstrate our solution on a 128-dimensional time series dataset of 1 million records, solving 274 trillion sorts at a sustained 1.3 Petaflop/s performance on the SuperMUC-NG system. © Springer Nature Switzerland AG 2020.

关键词： Time series

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LoRa-Powered Energy-Effcient Object Detection Mechanism in Edge Computing Nodes 6

LoRa-Powered Energy-Effcient Object Detection Mechanism in E...

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6th International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud), I-SMAC 2022

作者： Jindal, Anshul Jose, Jiby Mariya Benedict, Shajulin Gerndt, Michael Technical University Munich Computer Architecture and Parallel Systems Germany Indian Institute of Information Technology Kottayam Department of Computer Science and Engg. India

ISBN: (数字)9781665469418

ISBN: (纸本)9781665469418

The ongoing accomplishments in the decades-long realization of computer vision have infused new dimensions in various research areas such as smart mobility, smart healthcare, education, finance, and so forth. Research works relating to automated object detection, deep learning-assisted data pipelines, and energy-efficient end-to-end solutions have enabled newer perceptions among researchers, albeit the existence of challenges. This paper proposes an object detection system using energy-efficient Long Range (LoRA) communication media on edge nodes such as Raspberry Pi, Coral DevBoard, and Nvidia Jetson Nano. The proposed approach utilized energy-efficient methods to collaboratively offload object detection-related tasks such as capturing images, training images, and inferring objects across a compendium of computing nodes using LoRA. In addition, this research study has attempted to reveal the inference capabilities of images on three different edge nodes. The proposed work has achieved a power difference of at least 1.2 watts during the inference period of the deep learning models without challenging the prediction accuracy with respect to the base model. © 2022 IEEE.

关键词： Object detection

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Integration of Quantum Accelerators into HPC: Toward a Unified Quantum Platform

arXiv

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arXiv 2024年

作者： Elsharkawy, Amr Guo, Xiaorang Schulz, Martin Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale superlinearly with number of qubits, which is critical to support scalability efforts in QC hardware. Copyright © 2024, The Authors. All rights reserved.

关键词： Trapped ions

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