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arXiv 2019年

作者： Hamon, François P. Schreiber, Martin Minion, Michael L. Center for Computational Sciences and Engineering Lawrence Berkeley National Laboratory Berkeley United States Chair of Computer Architecture and Parallel Systems Technical University of Munich Germany Department of Applied Mathematics Lawrence Berkeley National Laboratory Berkeley United States

The modeling of atmospheric processes in the context of weather and climate simulations is an important and computationally expensive challenge. The temporal integration of the underlying PDEs requires a very large number of time steps, even when the terms accounting for the propagation of fast atmospheric waves are treated implicitly. Therefore, the use of parallel-in-time integration schemes to reduce the time-to-solution is of increasing interest, particularly in the numerical weather forecasting field. We present a multi-level parallel-in-time integration method combining the parallel Full Approximation Scheme in Space and Time (PFASST) with a spatial discretization based on Spherical Harmonics (SH). The iterative algorithm computes multiple time steps concurrently by interweaving parallel high-order fine corrections and serial corrections performed on a coarsened problem. To do that, we design a methodology relying on the spectral basis of the SH to coarsen and interpolate the problem in space. The methods are evaluated on the shallow-water equations on the sphere using a set of tests commonly used in the atmospheric flow community. We assess the convergence of PFASST-SH upon refinement in time. We also investigate the impact of the coarsening strategy on the accuracy of the scheme, and specifically on its ability to capture the high-frequency modes accumulating in the solution. Finally, we study the computational cost of PFASST-SH to demonstrate that our scheme resolves the main features of the solution multiple times faster than the serial schemes. Copyright © 2019, The Authors. All rights reserved.

关键词： Harmonic analysis

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IAD: Indirect anomalous VMMs detection in the cloud-based environment

arXiv

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arXiv 2021年

作者： Jindal, Anshul Shakhat, Ilya Cardoso, Jorge Gerndt, Michael Podolskiy, Vladimir Computer Architecture and Parallel Systems Technical University of Munich Garching Germany Huawei Munich Research Center Huawei Technologies Munich Germany University of Coimbra CISUC DEI Coimbra Portugal

Server virtualization in the form of virtual machines (VMs) with the use of a hypervisor or a Virtual Machine Monitor (VMM) is an essential part of cloud computing technology to provide infrastructureas-a-service (IaaS). A fault or an anomaly in the VMM can propagate to the VMs hosted on it and ultimately affect the availability and reliability of the applications running on those VMs. Therefore, identifying and eventually resolving it quickly is highly important. However, anomalous VMM detection is a challenge in the cloud environment since the user does not have access to the VMM. This paper addresses this challenge of anomalous VMM detection in the cloud-based environment without having any knowledge or data from VMM by introducing a novel machine learning-based algorithm called IAD: Indirect Anomalous VMMs Detection. This algorithm solely uses the VM's resources utilization data hosted on those VMMs for the anomalous VMMs detection. The developed algorithm's accuracy was tested on four datasets comprising the synthetic and real and compared against four other popular algorithms, which can also be used to the described problem. It was found that the proposed IAD algorithm has an average F1-score of 83.7% averaged across four datasets, and also outperforms other algorithms by an average F1-score of 11%. © 2021, CC BY.

关键词： Anomaly detection

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ReSim, a trace-driven, reconfigurable ILP processor simulator 09

ReSim, a trace-driven, reconfigurable ILP processor simulato...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Sotiria Fytraki Dionisios Pnevmatikatos Department of Electronic and Computer Engineering Technical University of Crete Chania Greece Parallel Systems Architecture Lab (PARSA) Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland FORTH-ICS Greece

ISBN: (纸本)9783981080155

Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration relies on extensive use of software simulation that when highly accurate is slow. In this paper we propose ReSim, a parameterizable ILP processor simulation acceleration engine based on reconfigurable hardware. We describe ReSim's trace-driven microarchitecture that allows us to simulate the operation of a complex ILP processor in a cycle serial fashion, aiming to simplify implementation complexity and to boost operating frequency. Being trace driven, ReSim can simulate timing in an almost ISA independent fashion, and supports all SimpleScalar ISAs, i.e. PISA, Alpha, etc. We implemented ReSim for the latest Xilinx devices. In our experiments with a 4-way superscalar processor ReSim achieves a simulation throughput of up to 28MIPS, and offers more than a factor of 5x improvement over the best reported ILP processor hardware simulators.

关键词： Hardware Instruction sets Application software Space exploration Acceleration Engines Microarchitecture Frequency Timing Throughput

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Leveraging Hybrid Classical-Quantum Methods for Efficient Load Rebalancing in HPC

Leveraging Hybrid Classical-Quantum Methods for Efficient Lo...

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High Performance Computing, Networking, Storage and Analysis, SC-W: Workshops of the International Conference for

作者： Justyna Zawalska Minh Chung Katarzyna Rycerz Laura Schulz Martin Schulz Dieter Kranzlmüller Institute of Computer Science AGH University of Krakow Krakow Poland Academic Computer Center CYFRONET AGH Krakow Poland Leibniz Supercomputing Centre (LRZ) Garching bei München Germany MNM-Team Ludwig-Maximilians-Universität München (LMU) Germany Chair for Computer Architecture and Parallel Systems Technical University of Munich (TUM) Germany

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

Load imbalance is a challenge for parallel applications in High Performance Computing (HPC). It is caused by processes having different execution times or load values, leading to idle or wait times at synchronization points, where faster processes must wait for the slowest process to catch up. To mitigate this issue, applications can employ load balancing (LB) strategies, which migrate load between processes to even out load. This is often referred to as the Load Rebalancing Problem (LRP). While many approaches solving the LRP exist, they can only be heuristics and hence further optimization potential exists. In our work, we turn to a novel approach by using hybrid classical-quantum approaches and present two versions of the constrained quadratic model for solving the LRP; the two differ in how they balance the number of qubits required with the types of applied constraints. We compare the quantum-based methods with classical methods using heuristic algorithms Greedy, Karmarkar–Karp, and ProactLB. We evaluate our approaches using imbalance ratio and speedup as metrics, as well as the number of migrated tasks to indicate overhead caused by migrations. Our results show that the quantum-based methods outperform the classic methods. For example, we need only 1/4 of the number of migrated tasks in a realistic use case compared with classical methods, particularly Greedy and KK, to balance the load.

关键词： Measurement Upper bound NP-hard problem High performance computing Heuristic algorithms Qubit Load management Synchronization Optimization Load modeling

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An Accurate and Hardware-Efficient Dual Spike Detector for Implantable Neural Interfaces

arXiv

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arXiv 2022年

作者： Guo, Xiaorang Shaeri, MohammadAli Shoaran, Mahsa Institute of Electrical and Micro Engineering Center for Neuroprosthetics EPFL Geneva1202 Switzerland Faculty of Electrical and Computer Engineering Technische Universität Dresden Dresden01069 Germany Chair of Computer Architecture and Parallel Systems Technische Universität München Garching85748 Germany

Spike detection plays a central role in neural data processing and brain-machine interfaces (BMIs). A challenge for future-generation implantable BMIs is to build a spike detector that features both low hardware cost and high performance. In this work, we propose a novel hardware-efficient and high-performance spike detector for implantable BMIs. The proposed design is based on a dual-detector architecture with adaptive threshold estimation. The dual-detector comprises two separate TEO-based detectors that distinguish a spike occurrence based on its discriminating features in both high and low noise scenarios. We evaluated the proposed spike detection algorithm on the Wave_Clus dataset. It achieved an average detection accuracy of 98.9%, and over 95% in high-noise scenarios, ensuring the reliability of our method. When realized in hardware with a sampling rate of 16kHz and 7-bits resolution, the detection accuracy is 97.4%. Designed in 65nm TSMC process, a 256-channel detector based on this architecture occupies only 682µm2/Channel and consumes 0.07µW/Channel, improving over the state-of-the-art spike detectors by 39.7% in power consumption and 78.8% in area, while maintaining a high accuracy. © 2022, CC BY.

关键词： Data handling

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Training Large Language Models for System-Level Test Program Generation Targeting Non-functional Properties

Training Large Language Models for System-Level Test Program...

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IEEE European Test Symposium (ETS)

作者： Denis Schwachhofer Peter Domanski Steffen Becker Stefan Wagner Matthias Sauer Dirk Pflüger Ilia Polian Institute of Computer Engineering and Computer Architecture University of Stuttgart Stuttgart Germany Institute of Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Technical University of Munich Heilbronn Germany Advantest Europe Boeblingen Germany

ISBN: (数字)9798350349320

ISBN: (纸本)9798350349337

System-Level Test (SLT) has been an integral part of integrated circuit test flows for over a decade and continues to be significant. Nevertheless, there is a lack of systematic approaches for generating test programs, specifically focusing on the non-functional aspects of the Device under Test (DUT). Currently, test engineers manually create test suites using commercially available software to simulate the end-user environment of the DUT. This process is challenging and laborious and does not assure adequate control over non-functional properties. This paper proposes to use Large Language Models (LLMs) for SLT program generation. We use a pre-trained LLM and fine-tune it to generate test programs that optimize non-functional properties of the DUT, e.g., instructions per cycle. Therefore, we use Gem5, a microarchitectural simulator, in conjunction with Reinforcement Learning-based training. Finally, we write a prompt to generate C code snippets that maximize the instructions per cycle of the given architecture. In addition, we apply hyperparameter optimization to achieve the best possible results in inference.

关键词： Training Knowledge engineering Codes Systematics Microarchitecture Process control Hyperparameter optimization

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Large Language Models to Generate System-Level Test Programs Targeting Non-functional Properties

arXiv

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arXiv 2024年

作者： Schwachhofer, Denis Domanski, Peter Becker, Steffen Wagner, Stefan Sauer, Matthias Pflüger, Dirk Polian, Ilia Institute of Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Advantest Europe Boeblingen Germany Institute of Computer Engineering and Computer Architecture University of Stuttgart Stuttgart Germany Technical University of Munich Heilbronn Germany

System-Level Test (SLT) has been a part of the test flow for integrated circuits for over a decade and still gains importance. However, no systematic approaches exist for test program generation, especially targeting non-functional properties of the Device under Test (DUT). Currently, test engineers manually compose test suites from off-the-shelf software, approximating the end-user environment of the DUT. This challenging and tedious task does not guarantee sufficient control over non-functional properties. This paper proposes Large Language Models (LLMs) to generate test programs. We take a first glance at how pre-trained LLMs perform in test program generation to optimize nonfunctional properties of the DUT. Therefore, we write a prompt to generate C code snippets that maximize the instructions per cycle of a super-scalar, out-of-order architecture in simulation. Additionally, we apply prompt and hyperparameter optimization to achieve the best possible results without further training. © 2024, CC BY.

关键词： Software testing

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Large Language Model-Based Optimization for System-Level Test Program Generation

Large Language Model-Based Optimization for System-Level Tes...

引用

IEEE International Symposium on Defect and Fault Tolerance in VLSI systems

ISBN: (数字)9798350366884

ISBN: (纸本)9798350366891

System-Level Test (SLT) is essential for testing integrated circuits, focusing on functional and non-functional properties of the Device under Test (DUT). Traditionally, test engineers manually create tests with commercial software to simulate the DUT's end-user environment. This process is both time-consuming and offers limited control over non-functional properties. This paper proposes Large Language Models (LLMs) enhanced by Structural Chain of Thought (SCoT) prompting, a temperature schedule, and a pool of previously generated snippets to generate high-quality code snippets for SLT. We repeatedly query the LLM for a better snippet using previously generated snippets as examples, thus creating an iterative optimization loop. This approach can automatically generate snippets for SLT that target specific non-functional properties, reducing time and effort. Our findings show that this approach improves the quality of the generated snippets compared to unstructured prompts containing only a task description.

关键词： Measurement Schedules Codes Temperature Process control Very large scale integration Software Optimization Nanotechnology Testing

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Multi-level spectral deferred corrections scheme for the shallow water equations on the rotating sphere

arXiv

引用

arXiv 2018年

作者： Hamona, François P. Schreiberb, Martin Miniond, Michael L. Center for Computational Sciences and Engineering Lawrence Berkeley National Laboratory Berkeley United States Department of Mathematics/Computer Science University of Exeter Exeter United Kingdom Computer Architecture and Parallel Systems Technical University of Munich Germany Department of Applied Mathematics Lawrence Berkeley National Laboratory Berkeley United States

Effcient time integration schemes are necessary to capture the complex processes involved in atmospheric ows over long periods of time. In this work, we propose a high-order, implicit-explicit numerical scheme that combines Multi-Level Spectral Deferred Corrections (MLSDC) and the Spherical Harmonics (SH) transform to solve the wave-propagation problems arising from the shallow-water equations on the rotating *** iterative temporal integration is based on a sequence of corrections distributed on coupled spacetime levels to perform a significant portion of the calculations on a coarse representation of the problem and hence to reduce the time-to-solution while preserving accuracy. In our scheme, referred to as MLSDCSH, the spatial discretization plays a key role in the efficiency of MLSDC, since the SH basis allows for consistent transfer functions between space-time levels that preserve important physical properties of the *** study the performance of the MLSDC-SH scheme with shallow-water test cases commonly used in numerical atmospheric modeling. We use this suite of test cases, which gradually adds more complexity to the nonlinear system of governing partial differential equations, to perform a detailed analysis of the accuracy of MLSDC-SH upon renement in time. We illustrate the stability properties of MLSDC-SH and show that the proposed scheme achieves up to eighth-order convergence in time. Finally, we study the conditions in which MLSDC-SH achieves its theoretical speedup, and we show that it can significantlyreduce the computational cost compared to single-level Spectral Deferred Corrections (SDC). Copyright © 2018, The Authors. All rights reserved.

关键词： Harmonic analysis

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Self-Awareness for Autonomous systems

引用

PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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