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检索条件"机构=Chair for Computer Science in Architecture"

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Cache aware instruction accurate simulation of a 3-D coastal ocean model on low power hardware

Cache aware instruction accurate simulation of a 3-D coastal...

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International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH)

作者： Dominik Schoenwetter Alexander Ditter Vadym Aizinger Balthasar Reuter Dietmar Fey Chair of Computer Science 3 (Computer Architecture) Friedrich-Alexander University Erlangen-Nürnberg (FAU) Erlangen Germany Chair of Applied Mathematics (AM1) Friedrich-Alexander University Erlangen-Nürnberg (FAU) Erlangen Germany

ISBN: (纸本)9781509058945

High level hardware simulation and modeling techniques matured significantly over the last years and have become more and more important in practice, e.g., in the industrial hardware development and automotive domain. Yet, there are many other challenging application areas such as numerical solvers for environmental or disaster prediction problems, e.g., tsunami and storm surge simulations, that could greatly profit from accurate and efficient hardware simulation. Such applications rely on complex mathematical models that are discretized using suitable numerical methods, and require a close collaboration between mathematicians and computer scientists to attain desired computational performance on current micro architectures and code parallelization techniques to produce accurate simulation results as fast as possible. This complex and detailed simulation requires a lot of time during preparation and execution. Especially the execution on non-standard or new hardware may be challenging and potentially error prone. In this paper, we focus on a high level simulation approach for determining accurate runtimes of applications using instruction accurate modeling and simulation. We extend the basic instruction accurate simulation technology from OVP using cache models in conjunction with a statistical cost function, which enables high precision and significantly better runtime predictions compared to the pure instruction accurate approach.

关键词： Hardware Numerical models Computational modeling computer architecture Mathematical model Solid modeling Predictive models

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architecture and Simulation of a Hybrid Memristive Multiplier Network using Redundant Number Representation

Architecture and Simulation of a Hybrid Memristive Multiplie...

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International Joint Conference on Neural Networks

作者： Dietmar Fey Jonathan Martschinke Friedrich-Alexander-University Erlangen-Nürnberg (FAU) Department of Computer Science Chair for Computer Architecture Martensstr. 3 91058 Erlangen Germany

ISBN: (纸本)9781479919611

The paper proposes an architecture for a multiplier-adder network that can be used for the design of a digital neuron cell. The core of the multiplier is based on a hybrid memristor network, in which digital CMOS logic is combined with multi-stable storing memristor devices. The multi-bit storing feature of memristors is favoured since it simplifies the realisation of ternary data. Using such a ternary number system in binary logic leads to a redundant number representation (RNR) that allows to speed up multiplications since they are reduced to adders working in constant time independent of the word length. For the verification of the multiplier architecture an own special simulation system was developed in C++ allowing flexible design and fast analogue simulation of large complex memristor networks. The superiority of the hybrid memristive architecture in terms of latency and bandwidth compared to an adder with carry-look-ahead technique is analytically shown.

关键词： Memristive Computing multi-state memristors signed-digit arithmetic multiplier networks Memristors architecture Building construction Multiplying circuits word length Number Representation adders Analog simulation binary logic CMOS logic counting system elastic design simulating Redundant Simulation Systems

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Smart sensor architectures for embedded biosignal analysis

Smart sensor architectures for embedded biosignal analysis

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Conference on Design and architectures for Signal and Image Processing

作者： Benjamin Pfundt Marc Reichenbach Björn Eskofier Dietmar Fey Department Computer Science Chair of Computer Architecture Department Computer Science Pattern Recognition Lab Friedrich-Alexander-University Erlangen-Nuremberg Germany

In many sports and medical applications small and wearable sensors are used that capture motion and physiological signals. Yet, commonly such sensor are only capable of acquiring raw data, which is afterwards transmitted to a smartphone or other mobile computing device where processing and classification is carried out. This results in limited usability because another device has to be worn. Moreover, high power consumption due to continuous transmission is a main disadvantage. Therefore, we propose a smart sensor approach that can alleviate these problems by carrying out the processing on the sensor itself. To house the processing schemes in the sensor node we developed a new computer architecture utilizing an FPGA and an ASIC. To show the benefits of the in-sensor processing, we chose two representative biosensor applications: a movement and fall detection system for the elderly and a swimming style recognition system for professional athletes. Compared to conventional approaches the same classification rate can be achieved while saving space, power, weight and setup costs.

关键词： computer architecture Accelerometers Feature extraction Intelligent sensors Monitoring Legged locomotion Pattern recognition

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Situation Recognition for Service Management Systems Using OWL 2 Reasoners

Situation Recognition for Service Management Systems Using O...

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IEEE Workshop on Context Modeling and Reasoning

作者： Waltenegus Dargie Eldora Julian Mendez Christoph Mobius Kateryna Rybina Veronika Thost Anni-Yasmin Turhan Chair of Computer Networks Institute of Systems Architecture Technische Universitat Dresden Chair for Automata Theory Institute for Theoretical Computer Science Technische Universitat Dresden

ISBN: (纸本)9781467350754

For service management systems the early recognition of situations that necessitate a rebinding or a migration of services is an important task. To describe these situations on differing levels of detail and to allow their recognition even if only incomplete information is available, we employ the ontology language OWL 2 and the reasoning services defined for it. In this paper we provide a case study on the performance of state of the art OWL 2 reasoning systems for answering class queries and conjunctive queries modeling the relevant situations for service rebinding or migration in the differing OWL 2 profiles.

关键词： OWL Servers Ontologies Cognition Runtime Hardware Power demand

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Object tracking as job-scheduling problem

Object tracking as job-scheduling problem

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ACM/IEEE International Conference on Distributed Smart Cameras, ICDSC

作者： Uwe Jaenen Henning Spiegelberg Lars Sommer Sebastian von Mammen Juergen Brehm Joerg Haehner Chair for Organic Computing Institute of Computer Science Universität Augsburg Augsburg Germany Department for System-and Computer-Architecture Leibniz Universität Hannover Hannover Germany

This paper establishes a connection between object tracking from a systems point of view and the job-scheduling or job-shop problem. Often, surveillance areas cannot be fully monitored by a set of smart cameras at any given point in time. Decisions have to be made, which objects are to be tracked. The computer vision aspects of object tracking have made substantial strides which permits for elaborately planning the monitoring jobs. In this paper, object tracking is handled as a job-scheduling problem. As a result, tracked objects are considered as scheduling jobs that rely on smart cameras as resources that follow according tracking policies. The presented job-scheduling approach is based on proactive quotations advertised by the jobs. The main advantages of this algorithm are the avoidance of negotiation chains and the acceptance of local non-optimal solutions to benefit the overall performance.

关键词： Cameras Trajectory Smart cameras Object tracking Surveillance Scheduling

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Akers's wavefront planner — One of the fastest stencil-based path planners on FPGAs

Akers's wavefront planner — One of the fastest stencil-base...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Michael Schmidt Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universitat Erlangen-Nuremberg Germany

The efficient and fast processing of path planning algorithms based on stencil codes is a great challenge. On the one hand, these iterative approaches are advantageous because of their regular processing pattern and the characteristic to avoid problems of other path planning methods, like local minima in potential field algorithms. On the other hand, they are computational- and data-intensive because of their high number of required iterations. By comparing several algorithms based on stencil codes, we found one of the fastest and most efficient path planners for realization on FPGAs, Akers's wavefront planner. A processing of 33 maps per second with a resolution of 1024×1024 is possible on a midsize Virtex-5 FPGA achieved through a column-based processing scheme combined with an efficient internal data storage.

关键词： computer architecture Microprocessors Field programmable gate arrays Path planning Clocks Registers Robots

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A speed-up study for a parallelized white light interferometry preprocessing algorithm on a virtual embedded multiprocessor system

A speed-up study for a parallelized white light interferomet...

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International Conference on architecture of Computing Systems (ARCS)

作者： Dominik Schoenwetter Max Schneider Dietmar Fey Chair of Computer Science 3 (Computer Architecture) Friedrich-Alexander-University of Erlangen-Nuremberg Erlangen Germany

Parallel computing has been a niche for scientific research in academia for decades. However, as common industrial applications become more and more performance demanding and raising the clock frequency of conventional single-core systems is hardly an option due to reaching technological limitations, efficient use of (embedded) multi-core CPUs and many-core platforms has become imperative. 3D surface analysis of objects using the white light interferometry presents one of such challenging applications. The goal in this article is to get an impression which speed-up for an established and parallelized white light interferometry preprocessing algorithm, called Contrast Method, is possible on an embedded system that works without any operating system. Therefore, we decided to use a virtual environment that is able to simulate embedded multi-core as well as many-core systems and that enables running real application code on the designed system. The results show, that a significant speedup is possible when using a many-core platform, instead of a design that only implements one single core, if the algorithm is parallelized for getting full advantage of the many-core design. Furthermore, an acceptable absolute run time is achievable.

关键词： Program processors Optical interferometry Interference Hardware Algorithm design and analysis Synchronization Multicore processing

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Heterogeneous computer architectures: An image processing pipeline for optical metrology

Heterogeneous computer architectures: An image processing pi...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Marc Reichenbach Ralf Seidler Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universität Erlangen-Nürnberg Germany

Industrial image processing tasks, especially in the domain of optical metrology, are becoming more and more complex. While in the recent years standard PC components were sufficient to fulfill the requirements, special architectures have to be used to build up high speed image processing systems today. For example for adaptive optical systems in large scale telescopes, the latency between capturing an image and steering the mirrors is critical for the quality of the resulting images. Commonly, the applied image processing algorithms consist of several tasks with different granularities and complexities. Therefore, we combined the advantages of multicore CPUs, GPUs, and FPGAs to build up a heterogeneous image processing pipeline for adaptive optical systems. Each used architecture is well-suited to solve a particular task efficiently. With the developed pipeline it is possible to achieve a high throughput and to reduce the latency of the whole steering system significantly.

关键词： Field programmable gate arrays computer architecture Image reconstruction Optical imaging Pipelines Adaptive optics

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A Generic VHDL Template for 2D Stencil Code Applications on FPGAs

A Generic VHDL Template for 2D Stencil Code Applications on ...

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IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW)

作者： Michael Schmidt Marc Reichenbach Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universitat Erlangen-Nuremberg Erlangen-Nuremberg Germany

The efficient realization of self-organizing systems based on 2D stencil code applications, like our developed Marching Pixel algorithms, is a great challenge. They are data-intensive and also computational-intensive, because often a high number of iterations is required. FPGAs are predestined for the realization of these algorithms. They are very flexible, allow a scalable parallel processing and have a moderate power consumption, even in high-performance versions. Therefore, FPGAs are highly qualified to make these applications also real-time capable. Our goal was to implement an efficient parameterizable buffering and parallel processing scheme for such operations in FPGAs, to process them as fast as possible. We developed a generic VHDL template which allows a scalable parallelization and pipelining of 2D stencil code applications in relation to application and hardware constraints.

关键词： computer architecture Microprocessors Field programmable gate arrays Pipeline processing Clocks Bandwidth Real time systems

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Automated Federation of Distributed Resources into User-Controlled Cloud Environments

Automated Federation of Distributed Resources into User-Cont...

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IEEE International Conference on Utility and Cloud Computing (UCC)

作者： Marc Mosch Hartmut Schweizer Stephan Gross Alexander Schill Department of Computer Science Institute of Systems Architecture Chair of Computer Networks Technische Universität Dresden Dresden Germany

Virtualization and broadband Internet connections enabled what is known today under the term cloud. Benefits like scalability and cost reduction by pay per use agreements are accompanied by potential harm to the users data. Since existing cloud solutions can be considered synonymous with unknown locations and potentially hostile environments security protection objectives can not be guaranteed. Motivated by cloud's potential we propose a way to get rid of this drawback. We present work in progress of an approach that enables users to benefit from cloud computing and retain data sovereignty by federating the users own resources. More precisely we present initial protocol design thoughts for this federation and an extension of the OCCI specification for the flexible description of own and foreign services.

关键词： Cloud computing Availability Protocols Encryption

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