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Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)

作者： Maël Gay Tobias Paxian Devanshi Upadhyaya Bernd Becker Ilia Polian Chair of Hardware Oriented Computer Science University of Stuttgart Stuttgart Germany Chair of Computer Architecture University of Freiburg Freiburg Germany

The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.

关键词： Circuit faults Integrated circuit modeling Ciphers Mathematical model Hardware Analytical models Tools

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Akers's wavefront planner — One of the fastest stencil-based path planners on FPGAs

Akers's wavefront planner — One of the fastest stencil-base...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Michael Schmidt Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universitat Erlangen-Nuremberg Germany

The efficient and fast processing of path planning algorithms based on stencil codes is a great challenge. On the one hand, these iterative approaches are advantageous because of their regular processing pattern and the characteristic to avoid problems of other path planning methods, like local minima in potential field algorithms. On the other hand, they are computational- and data-intensive because of their high number of required iterations. By comparing several algorithms based on stencil codes, we found one of the fastest and most efficient path planners for realization on FPGAs, Akers's wavefront planner. A processing of 33 maps per second with a resolution of 1024×1024 is possible on a midsize Virtex-5 FPGA achieved through a column-based processing scheme combined with an efficient internal data storage.

关键词： computer architecture Microprocessors Field programmable gate arrays Path planning Clocks Registers Robots

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An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels

An Optimized FPGA Implementation for a Parallel Path Plannin...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Michael Schmidt Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universitat Erlangen-Nuremberg Germany

Path Planning is one of the most computationally intensive tasks in robot systems and a challenge in dynamically changing environments. By means of FPGAs it is possible to process time-critical and data-intensive tasks in robot systems efficiently. We have developed a parallel path planning algorithm which is based on Marching Pixels, an organic computing principle. The algorithm is optimized for FPGA-based processing. A parallel implementation approach together with an efficient buffering of the map data allowed us to obtain a processing rate suitable for real time applications, even for higher resolutions. We achieved a processing rate of 80 maps per second for VGA resolution (640 × 480) on a midsize Virtex-5 FPGA.

关键词： Field programmable gate arrays Robots Pixel Path planning Skeleton Collision avoidance Clocks

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Embedded Parallel Computing Accelerators for Smart Control Units of Frequency Converters

Embedded Parallel Computing Accelerators for Smart Control U...

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ARCS 2016;29th International Conference on architecture of Computing Systems

作者： Steffen Vaas Marc Reichenbach Johannes Hofmann Thomas Stadelmayer Dietmar Fey Department of Computer Science Chair of Computer Architecture Friedrich-Alexander-University Erlangen-Nurnberg (FAU)

Classical frequency converters are designed as embedded devices optimized for a specific application-field. But in times of Industry 4.0 simple frequency converters change to smart control units and become more intelligent with analysis and reporting functions to build up smart grids in automation systems for reducing maintenance costs and increasing productivity. To realize these new functions, an evaluation is needed, which kind of computer architectures should be used for these new devices. Due to more complex algorithms, classical microcontrollers are not sufficient anymore. Therefore, we show in this paper, if and how microprocessors in smart control units can benefit from highly parallel hardware accelerators. Consequently, we propose to increase the performance of an ARM Cortex-A9 processor by using an Epiphany III E16 many-core processor as hardware accelerator for complex analysis tasks. Our results show, that a speedup of 1.78 can be achieved, while the power consumption is increased by only 9%.

关键词： Smart Sensors Many-Core Processor Heterogeneous Processor architecture Epiphany Parallella Embedded Preprocessing intelligent sensors Frequency converters control unit hardware accelerator Maintenance costs quad-issue processor Multi-core processors computer architecture Embedded device automation system Smart grids Power consumption macroprocessor Accelerators

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Interconnection of game worlds and physical environments in educational settings 09

Interconnection of game worlds and physical environments in ...

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Annual Workshop on Network and Systems Support for Games (NetGames)

作者： Raphael Zender Ulrike Lucke Dennis Maciuszek Alke Martens Institute of Computer Science Chair of Computer Architecture University of Rostock Rostock Germany Institute of Computer Science Chair of e-Learning and Cognitive Systems University of Rostock Rostock Germany

ISBN: (纸本)9781424456055

This article describes the use of a service-oriented architecture to bridge the gap between different environments in the context of game-based learning. This is verified by a combination of face-to-face scenarios with online tools and virtual worlds. Results of a prototypical evaluation are stated to verify the validity of the approach. Furthermore, the applications and possible extensions of the developed system are discussed.

关键词： Second Life Service oriented architecture Streaming media computer architecture Artificial intelligence Intelligent robots computer science Context-aware services Prototypes Virtual environment

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Machine learning approaches to understand the influence of urban environments on human’s physiological response

arXiv

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arXiv 2018年

作者： Ojha, Varun Kumar Griego, Danielle Kuliga, Saskia Bielik, Martin Buš, Peter Schaeben, Charlotte Treyer, Lukas Standfest, Matthias Schneider, Sven König, Reinhard Donath, Dirk Schmitt, Gerhard Chair of Information Architecture ETH Zürich Switzerland Chair of Computer Science in Architecture Bauhaus University Weimar Germany Computational Architecture Bauhaus University Weimar Germany

This research proposes a framework for signal processing and information fusion of spatial-temporal multi-sensor data pertaining to understanding patterns of humans physiological changes in an urban environment. The framework includes signal frequency unification, signal pairing, signal filtering, signal quantification, and data labeling. Furthermore, this paper contributes to human-environment interaction research, where a field study to understand the influence of environmental features such as varying sound level, illuminance, field-of-view, or environmental conditions on humans’ perception was proposed. In the study, participants of various demographic backgrounds walked through an urban environment in Zürich, Switzerland while wearing physiological and environmental sensors. Apart from signal processing, four machine learning techniques, classification, fuzzy rule-based inference, feature selection, and clustering, were applied to discover relevant patterns and relationship between the participants’ physiological responses and environmental conditions. The predictive models with high accuracies indicate that the change in the field-of-view corresponds to increased participant arousal. Among all features, the participants’ physiological responses were primarily affected by the change in environmental conditions and field-of-view. Copyright © 2018, The Authors. All rights reserved.

关键词： Feature extraction

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Internet Based Support for Architectural Planning Processes

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International Journal of Architectural Computing 2003年第3期1卷 361-373页

作者： Dirk Donath Katharina Richter Stefan Hansen Bauhaus-Universität Weimar InfAR Chair for Computer Science in Architecture Belvederer Allee 1 99421 Weimar Germany

As building projects become increasingly more complex, the number of project participants grows as does their spatial distribution. An effective decentralised work process and co-operation is of increasing importance. The global computer network, the internet, has great potential and recent times have seen the development of a variety of techniques in this field. The project described here is based upon this approach and also takes it a step further. A specific analysis of the topic and the subsequent identification of potential approaches formed the basis for an architectural application that brings the architect in contact with other project participants using the internet as a powerful yet simple and easy to use medium.

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Design reuse by modularity: a scalable dynamical (re)configurable multiprocessor system

Design reuse by modularity: a scalable dynamical (re)configu...

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EUROMICRO Conference

作者： R. Drechsler N. Drechsler E. Mackensen T. Schubert B. Becker Institute of Computer Science Chair of Computer Architecture Albert Ludwig University Freiburg im Breisgau Germany

We present a scalable, low cost multiprocessor system, which is used in the area of measurement, regulation, controlling and soft computing. The system is an example of extremely modular hardware/software design. Modular in this context means that we can easily change or optimize individually the components in the system for a given problem. One of the most important aspects of our multiprocessor system is the fact that the user can dynamically change the communication topology by software 'on-the-fly'. Thus, the hardware can be (re)configured during operation in less than 1 ms. By this, the CPUs in the multiprocessor system can communicate directly without any invention of another processor preventing the typical bottleneck in parallel systems. First applications have been implemented in an embedded controller for a vote counting machine, with emphasis on high data security and high throughput.

关键词： Multiprocessing systems Hardware Costs Area measurement Control systems Software design Context Topology Communication system software Application software

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A speed-up study for a parallelized white light interferometry preprocessing algorithm on a virtual embedded multiprocessor system

A speed-up study for a parallelized white light interferomet...

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International Conference on architecture of Computing Systems (ARCS)

作者： Dominik Schoenwetter Max Schneider Dietmar Fey Chair of Computer Science 3 (Computer Architecture) Friedrich-Alexander-University of Erlangen-Nuremberg Erlangen Germany

Parallel computing has been a niche for scientific research in academia for decades. However, as common industrial applications become more and more performance demanding and raising the clock frequency of conventional single-core systems is hardly an option due to reaching technological limitations, efficient use of (embedded) multi-core CPUs and many-core platforms has become imperative. 3D surface analysis of objects using the white light interferometry presents one of such challenging applications. The goal in this article is to get an impression which speed-up for an established and parallelized white light interferometry preprocessing algorithm, called Contrast Method, is possible on an embedded system that works without any operating system. Therefore, we decided to use a virtual environment that is able to simulate embedded multi-core as well as many-core systems and that enables running real application code on the designed system. The results show, that a significant speedup is possible when using a many-core platform, instead of a design that only implements one single core, if the algorithm is parallelized for getting full advantage of the many-core design. Furthermore, an acceptable absolute run time is achievable.

关键词： Program processors Optical interferometry Interference Hardware Algorithm design and analysis Synchronization Multicore processing

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ACTion: combining logic synthesis and technology mapping for MUX based FPGAs

ACTion: combining logic synthesis and technology mapping for...

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EUROMICRO Conference

作者： W. Gunther R. Drechsler Institute of Computer Science Chair of Computer Architecture Albert Ludwig University Freiburg im Breisgau Germany

Technology mapping for multiplexor (MUX) based field programmable gate arrays (FPGAs) has widely been considered. A new algorithm is proposed that applies techniques from logic synthesis during mapping. By this, the target technology is considered in the minimization process. Binary decision diagrams (BDDs) are used as an underlying data structure due to the close relation between BDDs and MUX netlists. The algorithm uses local don't cares obtained by a greedy algorithm. The mapping is sped up by computing signatures. A trade-off quality versus runtime can be specified by the user by setting different parameters. Experimental results comparing the approach to the best known results show improvements of more than 30% for area and 40% for delay for many instances.

关键词： Field programmable gate arrays Data structures Boolean functions Circuit synthesis Network synthesis Binary decision diagrams computer science computer architecture Programmable logic arrays Minimization

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