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Performance comparison of designated preprocessing white light interferometry algorithms on emerging multi- and many-core architectures

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Procedia computer science 2011年 4卷 2037-2046页

作者： Max Schneider Dietmar Fey Daniel Kapusi Torsten Machleidt Chair of Computer Science 3 (Computer Architecture) Friedrich-Alexander-University of Erlangen-Nuremberg ZBS e.V. Ilmenau Computer Graphics Group Technical University of Ilmenau GBS mbH Ilmenau

Parallel computing has been a niche for scientific research in academia for decades. However, as common industrial applications become more and more performance demanding and raising the clock frequency of conventional single-core systems is hardly an option due to reaching technological limitations, efficient use of multi-core CPUs has become imperative. 3D surface analysis of objects using the white light interferometry presents one of such computationally challenging applications. In this article three established preprocessing methods of white light interferometry data analysis are used to evaluate the suitability of three modern multi-core architectures - generic multi-core CPUs, GPGPUs and IBM's Cell BE. The results show that function offloading to GPGPUs, which offer independent memory and many hundreds of threads running in parallel, yields the highest performance compared to other systems. Furthermore, by outsourcing computational tasks to GPUs, the workload of other system resources, such as CPU or system memory, is reduced. This allows accelerated execution of other tasks, e.g. acquisition of images with higher frame rates.

关键词： White light interferometry Preprocessing Algorithms OpenMP IBM Cell BE CUDA GPGPU

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How to Speed up Embedded Multi-core Systems Using Locality Conscious Array Distribution for Loop Parallelization

How to Speed up Embedded Multi-core Systems Using Locality C...

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ARCS 2016;29th International Conference on architecture of Computing Systems

作者： Niklas Hehenkamp Remko van Wagensveld Dominik Schoenwetter Christian Facchi Ulrich Margull Dietmar Fey Ralph Mader Technische Hochschule Ingolstadt Chair of Computer Science 3 (Computer Architecture) Friedrich-Alexander-University Erlangen-Nurnberg (FAU) Continental Automotive GmbH

Safety critical embedded systems in the automotive domain will increasingly depend on parallel processing architectures. Since concurrency has largely been exploited on task level, future applications will feature growing proportions of parallel implementations on data level such as loop parallelism. Efficient memory utilization becomes inevitable to overcome future challenges facing the memory wall in modern computing. This work suggests an approach for data locality conscious memory accessing and data distribution implementations in embedded multi-core systems. The results have been validated by a case study on a modern Engine Control Unit focusing on the parallelization of widely spread array intensive loops.

关键词： Memory access Multi-core Loop parallelization Embedded system Embedded systems parallelization Loops data layer memory utilization Consciousness locality data Contraceptive Coil Concurrency Speeding embedding

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Towards Formalization of Enhanced Privacy ID (EPID)-based Remote Attestation in Intel SGX

Towards Formalization of Enhanced Privacy ID (EPID)-based Re...

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Euromicro Symposium on Digital System Design

作者： Muhammad Usama Sardar Do Le Quoc Christof Fetzer Chair of Systems Engineering Institute of Systems Architecture Faculty of Computer Science Technische Universität Dresden Dresden Germany

ISBN: (数字)9781728195353

ISBN: (纸本)9781728195360

Vulnerabilities in privileged software layers have been exploited with severe consequences. Recently, Trusted Execution Environments (TEEs) based technologies have emerged as a promising approach since they claim strong confidentiality and integrity guarantees regardless of the trustworthiness of the underlying system software. In this paper, we consider one of the most prominent TEE technologies, referred to as Intel Software Guard Extensions (SGX). Despite many formal approaches, there is still a lack of formal proof of some critical processes of Intel SGX, such as remote attestation. To fill this gap, we propose a fully automated, rigorous, and sound formal approach to specify and verify the Enhanced Privacy ID (EPID)-based remote attestation in Intel SGX under the assumption that there are no side-channel attacks and no vulnerabilities inside the enclave. The evaluation indicates that the confidentiality of attestation keys is preserved against a Dolev-Yao adversary in this technology. We also present a few of the many inconsistencies found in the existing literature on Intel SGX attestation during formal specification.

关键词： Software Cryptography Computational modeling Protocols Privacy Testing

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architecture and Simulation of a Hybrid Memristive Multiplier Network using Redundant Number Representation

Architecture and Simulation of a Hybrid Memristive Multiplie...

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International Joint Conference on Neural Networks

作者： Dietmar Fey Jonathan Martschinke Friedrich-Alexander-University Erlangen-Nürnberg (FAU) Department of Computer Science Chair for Computer Architecture Martensstr. 3 91058 Erlangen Germany

ISBN: (纸本)9781479919611

The paper proposes an architecture for a multiplier-adder network that can be used for the design of a digital neuron cell. The core of the multiplier is based on a hybrid memristor network, in which digital CMOS logic is combined with multi-stable storing memristor devices. The multi-bit storing feature of memristors is favoured since it simplifies the realisation of ternary data. Using such a ternary number system in binary logic leads to a redundant number representation (RNR) that allows to speed up multiplications since they are reduced to adders working in constant time independent of the word length. For the verification of the multiplier architecture an own special simulation system was developed in C++ allowing flexible design and fast analogue simulation of large complex memristor networks. The superiority of the hybrid memristive architecture in terms of latency and bandwidth compared to an adder with carry-look-ahead technique is analytically shown.

关键词： Memristive Computing multi-state memristors signed-digit arithmetic multiplier networks Memristors architecture Building construction Multiplying circuits word length Number Representation adders Analog simulation binary logic CMOS logic counting system elastic design simulating Redundant Simulation Systems

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Lower bound sifting for MDDs

Lower bound sifting for MDDs

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International Symposium on Multiple-Valued Logic

作者： D. Jankovic W. Gunther R. Drechsler Faculty of Electronic Engineering University of Nis Nis Yugoslavia Institute of Computer Science Chair of Computer Architecture Albert Ludwig University Freiburg im Breisgau Germany

Decision Diagrams (DDs) are a data structure for the representation and manipulation of discrete logic functions often applied in VLSI CAD. Common DDs to represent Boolean functions are Binary Decision Diagrams (BDDs). Multiple-valued logic functions can be represented by multiple-valued Decision Diagrams (MDDs). The effiency of a DD representation strongly depends on the variable ordering; the size may vary from linear to exponential. Finding a good ordering is an NP-hard problem that has received considerable attention resulting in many minimization methods. Sifting is the most popular heuristic for dynamic DD minimization. In this paper we give lower bounds for sifting of MDDs. Based on them, both lower bound sifting for MDD minimization and lower bound group sifting for BDD minimization are proposed. By the computation of good lower bounds large parts of the search space can be pruned resulting in very fast computations. This is demonstrated by experimental results.

关键词： Boolean functions Data structures Runtime Logic functions Very large scale integration Minimization methods Binary decision diagrams computer science computer architecture

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Object tracking as job-scheduling problem

Object tracking as job-scheduling problem

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ACM/IEEE International Conference on Distributed Smart Cameras, ICDSC

作者： Uwe Jaenen Henning Spiegelberg Lars Sommer Sebastian von Mammen Juergen Brehm Joerg Haehner Chair for Organic Computing Institute of Computer Science Universität Augsburg Augsburg Germany Department for System-and Computer-Architecture Leibniz Universität Hannover Hannover Germany

This paper establishes a connection between object tracking from a systems point of view and the job-scheduling or job-shop problem. Often, surveillance areas cannot be fully monitored by a set of smart cameras at any given point in time. Decisions have to be made, which objects are to be tracked. The computer vision aspects of object tracking have made substantial strides which permits for elaborately planning the monitoring jobs. In this paper, object tracking is handled as a job-scheduling problem. As a result, tracked objects are considered as scheduling jobs that rely on smart cameras as resources that follow according tracking policies. The presented job-scheduling approach is based on proactive quotations advertised by the jobs. The main advantages of this algorithm are the avoidance of negotiation chains and the acceptance of local non-optimal solutions to benefit the overall performance.

关键词： Cameras Trajectory Smart cameras Object tracking Surveillance Scheduling

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A Parallel-friendly Majority Gate to Accelerate In-memory Computation

A Parallel-friendly Majority Gate to Accelerate In-memory Co...

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International Conference on Application Specific Systems (ASAP), architectures and Processors

作者： John Reuben Stefan Pechmann Chair of Computer Science 3 - Hardware Architecture Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Erlangen Germany Chair of Communications Electronics Universität Bayreuth Bayreuth Germany

ISBN: (数字)9781728171470

ISBN: (纸本)9781728172798

Efforts to combat the ‘von Neumann bottleneck’ have been strengthened by Resistive RAMs (RRAMs), which enable computation in the memory array. Majority logic can accelerate computation when compared to NAND/NOR/IMPLY logic due to it’s expressive power. In this work, we propose a method to compute majority while reading from a transistor-accessed RRAM array. The proposed gate was verified by simulations using a physics-based model (for RRAM) and industry standard model (for CMOS sense amplifier) and, found to tolerate reasonable variations in the RRAMs’ resistive states. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. The parallel-friendly nature of the proposed gate is exploited to implement an eight-bit parallel-prefix adder in memory array. The proposed in-memory adder could achieve a latency reduction of 70% and 50% when compared to IMPLY and NAND/NOR logic-based adders, respectively.

关键词： Logic gates Resistance Sensors Transistors Adders Inverters Delays

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Exploring the Use of WebAssembly in HPC

arXiv

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arXiv 2023年

作者： Chadha, Mohak Krueger, Nils John, Jophin Jindal, Anshul Gerndt, Michael Benedict, Shajulin Chair of Computer Architecture and Parallel Systems Technische Universität München Germany Department of Computer Science and Engg. Indian Institute of Information Technology Kerala Kottayam India

Containerization approaches based on namespaces offered by the Linux kernel have seen an increasing popularity in the HPC community both as a means to isolate applications and as a format to package and distribute them. However, their adoption and usage in HPC systems faces several challenges. These include difficulties in unprivileged running and building of scientific application container images directly on HPC resources, increasing heterogeneity of HPC architectures, and access to specialized networking libraries available only on HPC systems. These challenges of container-based HPC application development closely align with the several advantages that a new universal intermediate binary format called WebAssembly (Wasm) has to offer. These include a lightweight userspace isolation mechanism and portability across operating systems and processor architectures. In this paper, we explore the usage of Wasm as a distribution format for MPI-based HPC applications. To this end, we present MPIWasm, a novel Wasm embedder for MPI-based HPC applications that enables high-performance execution of Wasm code, has low-overhead for MPI calls, and supports high-performance networking interconnects present on HPC systems. We evaluate the performance and overhead of MPIWasm on a production HPC system and AWS Graviton2 nodes using standardized HPC benchmarks. Results from our experiments demonstrate that MPIWasm delivers competitive native application performance across all scenarios. Moreover, we observe that Wasm binaries are 139.5x smaller on average as compared to the statically-linked binaries for the different standardized benchmarks. Copyright © 2023, The Authors. All rights reserved.

关键词： Containers

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Cache aware instruction accurate simulation of a 3-D coastal ocean model on low power hardware

Cache aware instruction accurate simulation of a 3-D coastal...

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International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH)

作者： Dominik Schoenwetter Alexander Ditter Vadym Aizinger Balthasar Reuter Dietmar Fey Chair of Computer Science 3 (Computer Architecture) Friedrich-Alexander University Erlangen-Nürnberg (FAU) Erlangen Germany Chair of Applied Mathematics (AM1) Friedrich-Alexander University Erlangen-Nürnberg (FAU) Erlangen Germany

ISBN: (纸本)9781509058945

High level hardware simulation and modeling techniques matured significantly over the last years and have become more and more important in practice, e.g., in the industrial hardware development and automotive domain. Yet, there are many other challenging application areas such as numerical solvers for environmental or disaster prediction problems, e.g., tsunami and storm surge simulations, that could greatly profit from accurate and efficient hardware simulation. Such applications rely on complex mathematical models that are discretized using suitable numerical methods, and require a close collaboration between mathematicians and computer scientists to attain desired computational performance on current micro architectures and code parallelization techniques to produce accurate simulation results as fast as possible. This complex and detailed simulation requires a lot of time during preparation and execution. Especially the execution on non-standard or new hardware may be challenging and potentially error prone. In this paper, we focus on a high level simulation approach for determining accurate runtimes of applications using instruction accurate modeling and simulation. We extend the basic instruction accurate simulation technology from OVP using cache models in conjunction with a statistical cost function, which enables high precision and significantly better runtime predictions compared to the pure instruction accurate approach.

关键词： Hardware Numerical models Computational modeling computer architecture Mathematical model Solid modeling Predictive models

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Multiobjective programming for type-2 hierarchical fuzzy inference trees

arXiv

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arXiv 2017年

作者： Ojha, Varun Kumar Snášel, Václav Abraham, Ajith Chair of Information Architecture Eth Zurich Zurich Switzerland Dept. of Computer Science Technical University of Ostrava Machine Intelligence Research Labs Washington United States

This paper proposes a design of hierarchical fuzzy inference tree (HFIT). An HFIT produces an optimum tree-like structure. Specifically, a natural hierarchical structure that accommodates simplicity by combining several low-dimensional fuzzy inference systems (FISs). Such a natural hierarchical structure provides a high degree of approximation accuracy. The construction of HFIT takes place in two phases. Firstly, a nondominated sorting based multiobjective genetic programming (MOGP) is applied to obtain a simple tree structure (low model's complexity) with a high accuracy. Secondly, the differential evolution algorithm is applied to optimize the obtained tree's parameters. In the obtained tree, each node has a different input's combination, where the evolutionary process governs the input's combination. Hence, HFIT nodes are heterogeneous in nature, which leads to a high diversity among the rules generated by the HFIT. Additionally, the HFIT provides an automatic feature selection because it uses MOGP for the tree's structural optimization that accept inputs only relevant to the knowledge contained in data. The HFIT was studied in the context of both type-1 and type-2 FISs, and its performance was evaluated through six application problems. Moreover, the proposed multiobjective HFIT was compared both theoretically and empirically with recently proposed FISs methods from the literature, such as McIT2FIS, TSCIT2FNN, SIT2FNN, RIT2FNS-WB, eT2FIS, MRIT2NFS, IT2FNN-SVR, etc. From the obtained results, it was found that the HFIT provided less complex and highly accurate models compared to the models produced by most of the other methods. Hence, the proposed HFIT is an efficient and competitive alternative to the other FISs for function approximation and feature selection. Copyright © 2017, The Authors. All rights reserved.

关键词： Feature extraction

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