The amount of die area consumed by scan chains and scan control circuit can range from 15%∼30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on t...
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The notion of the mobile agent has been around for over a decade in order to capture the new form of computation in communication networks. A mobile agent is a computing entity which can move around different hosts on...
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In 1D signal processing local energy and phase can be determined by the analytic signal. Local energy, phase and orientation of 2D signals can be analyzed by the monogenic signal for all i(ntrinsic)1D signals in an ro...
In 1D signal processing local energy and phase can be determined by the analytic signal. Local energy, phase and orientation of 2D signals can be analyzed by the monogenic signal for all i(ntrinsic)1D signals in an rotational invariant way by the generalized Hilbert transform. In order to analyze both i1D and i2D signals in one framework the main idea of this contribution is to lift up 2D signals to the higher dimensional conformal space in which the original signal can be analyzed with more degrees of freedom by the generalized Hilbert transform on the unit sphere. An appropriate embedding of 2D signals on the unit sphere results in an extended feature space spanned by local energy, phase, orientation/direction and curvature. In contrast to classical differential geometry, local curvature can now be determined by the generalized Hilbert transform in monogenic scale space without any derivatives.
A novel method which entirely resides inside conformal geometric algebra (CGA) is presented estimating the pose of a camera from one image of a known object. At first, subproblems covering only three feature points ar...
A novel method which entirely resides inside conformal geometric algebra (CGA) is presented estimating the pose of a camera from one image of a known object. At first, subproblems covering only three feature points are solved and globally assessed. The object model is accordingly pruned and rigidly fitted to corresponding projection rays by evaluating a succinct CGA expression which emerged from a purely geometric approach. It results a set of 3‐point poses each given by a motor. These spinor elements of CGA embody rigid body motions from the manifold SE(3). The poses are then to be averaged according to their quality. This is the second aspect of this work as the respective motors do not come from a linear space and averaging must be carried out appropriately. For this purpose, a technique called weighted intrinsic mean is used.
Allocation order is the best for locality, which slide mark compact algorithm is based on. But traditional design made the algorithm's overhead too large. We proposed a fast slide mark compact algorithm, which red...
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Allocation order is the best for locality, which slide mark compact algorithm is based on. But traditional design made the algorithm's overhead too large. We proposed a fast slide mark compact algorithm, which reduces the overhead by mark bit table, live block pool and offset table. The results show that it achieves up to 8.9% speedup in industry-standard benchmark SPEC JVM98 on the Pentium 4, 11% improvement in dtlb miss numbers and 13.6% reduce with L2 cache miss numbers.
Community satisfaction has become a crucial aspect to measure success of emerging community information systems. Thus, we propose a community success model (CSM) based on the seminal DeLone & McLean IS success mod...
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ISBN:
(纸本)9781424418657
Community satisfaction has become a crucial aspect to measure success of emerging community information systems. Thus, we propose a community success model (CSM) based on the seminal DeLone & McLean IS success model, gaming communities are part of our new media culture, entertaining people of all ages with online and video games. As a proof of concept, we apply our CSM to gaming communities. CSM was evaluated in our university lab course ldquogaming communitiesrdquo. We analyze requirements from gaming communities and offer support to those communities by assessing the potential community satisfaction of prototypical solutions realized in the course through automatic monitoring of the service use and a questionnaire tool.
The characteristics of advanced integrated circuit technologies require architects to look for new ways to utilize large numbers of gates and mitigate the effects of high interconnect delays. Chip multiprocessors (CMP...
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The characteristics of advanced integrated circuit technologies require architects to look for new ways to utilize large numbers of gates and mitigate the effects of high interconnect delays. Chip multiprocessors (CMPs) exploit increasing transistor counts by placing multiple processors on a single die. As the chip multiprocessors (CMPs) have become the trend of high performance microprocessors, the target workloads become more and more diversified. Due to the wire delay problem and diversity of applications, neither private nor shared caches can provide both large capacity and fast access in CMPs. A novel CMP cache design, the heterogeneous CMP cache (HCC) is presented, in which chips are constructed by tiles of two different categories. L2 caches of private tiles provide lowest hit latency and L2 cache of shared tiles increases the effective cache capacity for shared data. Incorporating indirect-index cache technology to share capacity between different hierarchies, HCC provide a both capacity-effective and access-fast on-chip memory subsystem. Detailed full-system simulations are used to analyze the HCC performance for various programs, including SPEC CPU2000, SPLASH2 and commercial workloads. The result shows that HCC improves performance by 16% for single-threaded benchmarks and 9% for multi-thread benchmarks. HCC is easy to implement and the design ideas will be used in the future multi-core processors of Godson series.
To efficiently and appropriately integrate daylighting strategies in their projects, building designers need reliable methods to address issues such as daily and seasonal variations or the balance between sufficient i...
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ISBN:
(纸本)9781905254347
To efficiently and appropriately integrate daylighting strategies in their projects, building designers need reliable methods to address issues such as daily and seasonal variations or the balance between sufficient illumination with visual and thermal comfort aspects. This integration must also happen early in the design process to have a significant impact on energy savings and ultimate building performance. This paper proposes to address this need by fulfilling three major objectives: support the design process using a goal-oriented approach based on iterative design improvement suggestions;provide climate-based annual metrics in a visual and synthesized form;and relate quantitative and qualitative performance criteria thanks to a novel interface for browsing daylighting analysis data in various forms. A methodology to achieve these objectives is described here as the Lightsolve approach.
Universities (the universal research-providers) as well as research funders (public and private) are beginning to make it part of their mandates to ensure not only that researchers conduct and publish peer-reviewed re...
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Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrong-path (i.e. mis-speculated) instructions. These schemes assume that all wrong-path instruct...
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ISBN:
(纸本)9781424420704
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrong-path (i.e. mis-speculated) instructions. These schemes assume that all wrong-path instructions are useless for processor performance and try to eliminate the execution of all wrong-path instructions. However, wrong-path memory references can be useful for performance by providing prefetching benefits for later correct-path operations. Therefore, eliminating wrong-path instructions without considering the usefulness of wrong-path execution can significantly reduce performance as well as increase overall energy consumption. This paper proposes a comprehensive, low-cost speculation control mechanism that takes into account the usefulness of wrong-path execution, while effectively reducing the energy consumption due to useless wrong-path instructions. One component of the mechanism is a simple, novel wrong-path usefulness predictor (WPUP) that can accurately predict whether or not wrong-path execution will be beneficial for performance. The other component is a novel branch-count based fetch gating scheme that requires very little hardware cost to detect if the processor is on the wrong path. The key idea of our speculation control mechanism is to gate the processor pipeline only if (1) the number of outstanding branches is above a dynamically-determined threshold and (2) the WPUP predicts that wrong-path execution will not be beneficial for performance. Our results show that our proposal eliminates most of the performance loss incurred by fetch gating mechanisms that assume wrong-path execution is useless, thereby both improving performance and reducing energy consumption while requiring very little (51- byte) hardware cost.
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