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Performance evaluation of the multimedia router with MPEG-2 video traffic 3rd

Performance evaluation of the multimedia router with MPEG-2 ...

3rd International Workshop on Communication, architecture and Applications for Network-based Parallel Computing , CANPC 1999

作者： Caminero, Blanca Quiles, Francisco J. Duato, José Love, Damon S. Yalamanchili, Sudhakar Dept. of Computer Science Escuela Politécnica Superior de Albacete Universidad de Castilla La ManchaAlbacete02071 Spain Dept. of Information Systems and Computer Architecture Universidad Politécnica de Valencia P.O.B. 22012 Valencia46071 Spain School of Electrical and Computer Engineering Georgia Institute of Technology AtlantaGA30332-0250 Georgia

ISBN: (纸本)3540659153

The Multimedia Router (MMR) architecture is aimed at providing QoS to multimedia traffic in a local area environment, while retaining a compact and simple design. In this paper, we show some preliminary performance evaluation results. The workload was composed of a mix of synthetic CBR traffic and semi-synthetic VBR traffic. The latter was obtained from real MPEG-2 video sequences. We show that, with a simple scheduling algorithm, amenable for single-chip implementation, the link bandwidth utilization is quite satisfactory, while still providing acceptable delays to both CBR and VBR traffic. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Scheduling algorithms

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Evaluating register allocation and instruction scheduling techniques in out-of-order issue processors

Evaluating register allocation and instruction scheduling te...

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： M.G. Valluri R. Govindarajan Laboratory for Computer Architecture ECE Department University of Technology Austin TX USA Supercomputer Education and Research Centre Department of Computer Science and Automation Indian Institute of Science Bangalore India

The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the context of out-of-order issue processors. Such a study is interesting as the dynamic instruction ordering and register renaming support mechanisms in out-of-order issue processors are similar in spirit to what the complex register allocation and instruction scheduling techniques do at compile-time. We evaluated four existing techniques, namely postpass scheduling, prepass scheduling, parallel interference graph, and integrated prepass scheduling methods. Our initial experimental results reveal that for o-o-o issue processors the focus should be on reducing the register pressure/spill code than exposing the parallelism at compiling time.

关键词： Out of order Registers Processor scheduling VLIW Laboratories computer architecture Supercomputers computer science education computer science Automation

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Efficient parallelisation using combined loop and data transformations

Efficient parallelisation using combined loop and data trans...

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： M.F.P. O'Boyle P.M.W. Knijnenburg Institute for Computing Systems Architecture University of Edinburgh Edinburgh UK Department of Computer Science Leiden University Leiden Netherlands

The paper attempts to minimise parallelisation overhead on distributed shared memory machines, such as the SGi Origin 2000, by the combination of non-singular loop and data transformations. We show that conflicting requirements on a loop transformation may be resolved by using a data transformation and vice-versa. We develop optimisation criteria for locality, synchronisation and communication and show that neither loop nor data transformations can be solely used for efficient parallelisation. This leads to the development of a novel global optimisation heuristic which is applied to 3 SPEC kernels where it is shown to outperform techniques solely based on loop or data transformations and to give significant improvement over an existing state-of-the-art commercial auto-paralleliser.

关键词： Parallel processing computer architecture computer science Kernel Costs Delay Program processors Context Parallel machines Spatial resolution

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MMR: a high-performance MultiMedia Router-architecture and design trade-offs

MMR: a high-performance MultiMedia Router-architecture and d...

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IEEE Symposium on High-Performance computer architecture

作者： J. Duato S. Yalamanchili M.B. Caminero D. Love F.J. Quiles Department of Information Systems and Computer Architecture Universidad Politecnica de Valencia Valencia Spain School of Electrical and Computer Engineering Georgia Institute of Technology Department of Computer Science Escuela Politecnica Superior de Albacete Spain

This paper presents the architecture of a router designed to efficiently support traffic generated by multimedia applications. The router is targeted for use in clusters and LANs rather than in WANs, the latter being served by communication substrates such as ATM. The distinguishing features of the proposed router architecture are the use of small fixed-size buffers, a large number of virtual channels, link-level virtual channel flow control, support for dynamic modification of connection bandwidth and priorities, and coordinated scheduling of connections across all output channels. The paper begins with a discussion of the design choices and architectural trade-offs made in the current MultiMedia Router (MMR) project. The performance evaluation section presents some preliminary results of the coordinated scheduling of constant bit rate (CBR) traffic streams.

关键词： Bandwidth Delay Streaming media Quality of service Bit rate Local area networks Telecommunication traffic Application software Communication system control Cost accounting

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Sensor-based obstacle modeling in configuration space for manipulator motion planning

Sensor-based obstacle modeling in configuration space for ma...

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International Workshop on Robot Motion and Control (RoMoCo)

作者： Wei Li Zusbun Chen F.M. Wahl K.R. Kozlowski Department of Computer Science and Technology Tsinghua University Beijing China Institute for Robotics and Process Control Technical University of Braunschweig Brunswick Germany Chair of Control Robotics and Computer Science Poznań University of Technology Poznan Poland

Presents an approach to sensor-based obstacle modeling in a configuration space for manipulator motion planning in unknown environments. In order to achieve this objective, an efficient algorithm is used to fast map obstacles based on defined fundamental obstacles in the workspace and their images in the configuration space. A robotic manipulator is assumed to be equipped with distance sensors to detect obstacles in the local region. By computation of the critical points of an obstacle based on information acquired by the distance sensors, an obstacle model in the configuration space is constructed. By using this sensor-based configuration space modeling, robot motion planning in unknown environments can be performed in realistic time frames.

关键词： Manipulators Orbital robotics Motion planning Robot sensing systems Space technology Computational geometry Process planning Technology planning computer science Solid modeling

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The Paderborn university BSP (PUB) library-design, implementation and performance

The Paderborn university BSP (PUB) library-design, implement...

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International Symposium on Parallel Processing

作者： O. Bonorden B. Juurlink I. Von Otte I. Rieping Heinz Nixdorf Institute and Department of Computer Science Paderborn University Paderborn Germany Laboratory of Computer Architecture and Digital Techniques Department of Electrical Engineering Delft Technical University Delft Netherlands

The Paderborn University BSP (PUB) library is a parallel C library based on the BSP model. The basic library supports buffered and unbuffered asynchronous communication between any pair of processors, and a mechanism for synchronizing the processors in a barrier style. In addition, it provides routines for collective communication on arbitrary subsets of processors, partition operations, and a zero-cost synchronization mechanism. Furthermore, some techniques used in its implementation deviate significantly from the techniques used in other BSP libraries.

关键词： Libraries System recovery Costs Electrical capacitance tomography Workstations Parallel programming computer architecture Electronic mail Safety Yarn

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High performance sockets and RPC over virtual interface (VI) architecture 3rd

High performance sockets and RPC over virtual interface (VI)...

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3rd International Workshop on Communication, architecture and Applications for Network-based Parallel Computing , CANPC 1999

作者： Shah, Hemal V. Pu, Calton Madukkarumukumana, Rajesh S. M/S CO3-202 Server Architecture Lab Intel Corporation 5200 N.E. Elam Young Pkwy HillsboroOR97124 United States Department of Computer Science and Engineering Oregon Graduate Institute of Science and Technology P.O. Box 91000 PortlandOR97291 United States

ISBN: (纸本)3540659153

Standard user-level networking architecture such as Virtual Interface (VI) architecture enables distributed applications to perform low overhead communication over System Area Networks (SANs). This paper describes how high-level communication paradigms like stream sockets and remote procedure call (RPC) can be efficiently built over user-level networking architectures. To evaluate performance benefits for standard client-server and multi-threaded environments, our focus is on off-the-shelf sockets and RPC interfaces and commercially available VI architecture based SANs. The key design techniques developed in this research include credit-based flow control, decentralized user-level protocol processing, caching of pinned communication buffers, and deferred processing of completed send operations. The one-way bandwidth achieved by stream sockets over VI architecture was 3 to 4 times better than the same achieved by running legacy protocols over the same interconnect. On the same SAN, high-performance stream sockets and RPC over VI architecture achieve significantly better (between 2-3x) latency than conventional stream sockets and RPC over standard network protocols in Windows NTTM 4.0 environment. Furthermore, our high-performance RPC transparently improved the network performance of Distributed Component Object Model (DCOM) by a factor of 2 to 3. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Network architecture

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Designing the user interface for pen and speech multimedia applications

Designing the user interface for pen and speech multimedia a...

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Conference on Human Factors in Computing Systems, CHI EA 1999

作者： Larson, James A. Oviatt, Sharon Ferro, David L. Intel Architecture Labs. 2111 N.E. 25 th Avenue Hillsboro OR 97124-5961 United States Center for Human-Computer Communication Oregon Graduate Institute of Science and Tech. P.O. Box 91000 Portland OR 97291-1000 United States Unisys Natural Language 2476 Swedesford Road Malvern PA 19355 United States

This workshop will bring together a small group of researchers and practitioners to discuss how to design applications with both a verbal user interface (the user hears and speaks to the application) and a visual user interface (the user draws/writes and sees the application). Our goal is to better understand the issues that face designers of applications with multimedia interfaces integrating both visual and verbal interaction styles, exchange ideas and information, and increase communication among the diverse groups involved in multimedia interfaces.

关键词： User interfaces

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Definition of evaluation criteria for system development acquisition modeling and simulation

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NAVAL ENGINEERS JOURNAL 1999年第1期111卷 55-64页

作者： Leite, MJ Mensh, DR Michael J. Leite:is a Principal Engineer with PRC Inc. a division of Litton Industries. He supports combat system engineering for theater air and missile defense. His other tasks have included the command and control for the AEGIS shipbuilding program systems engineering for the 21st Century Surface Combatant combat system survivability and the development of NATO standardization agreements for naval ordnance. He was previously a Senior Engineer with San Diego Gas & Electric with responsibility for its energy application and lighting programs. Prior to joining SDG&E Mr. Leite was a commissioned officer in the U.S. Navy where he served in operations and engineering assignments. Following active duty he accepted a Naval Reserve commission and has retired with the rank of Captain. His assignments included command operational and engineering tours. Mr. Leite has also served as an expert witness in admiralty and engineering matters. He is a gradate of the University of California Berkeley with a Bachelor of Science Degree in Engineering and also holds a Masters Degree in Business Administration from National University in San Diego. Mr. Leite is a Registered Professional Engineer in the States of California and Minnesota. Mr. Leite is a member of ASNE ASCE MORS the Illuminating Engineering Society and the U.S. Naval institute. Dennis Roy Mensh:is a Senior Engineer with PRC Inc. a division of Litton Industries in Crystal City VA where he supports modeling and simulation tasking for combat systems. He received BS and MS degrees in applied Physics from Lopola College in Baltimore MD and the American University in Washington DC. He has also completed the course work towards a Ph.D. degree in computer science specializing in the fields of Operations Reseurch Anabsis Systems Analysis and Computer Modeling and Simulation. Previously he was employed at the White Oak Laboratory of the Naval Surface Warfare Carter in Silver Spring MD where he worked in the areas of naval sensor and weapon system analysis

This paper defines, develops and examines a set of generic analysis tools that can be applied to Models and Simulations at the Systems Engineering level of fidelity. The tools examine the performance and effectiveness of Sensors;Weapons;and Battle Management, Command, Control, Communications, computers, and Intelligence ((BMCI)-I-4) systems and equipment. The Measures of Performance (MOPs), Measures of Effectiveness (MOEs) and Measures of Force Effectiveness (MOFEs) were extracted from the Modular Command and Control Structure Paradigm which was developed at the Naval Postgraduate School. The paradigm provides for the development of evaluation criteria (MOPs, MOEs, and MOFEs) in a framework that ensures the traceability of system performance and effectiveness to the system operational requirements as specified in the Operational Requirements Document (ORD). Also, the analysis tools provide insight and valid estimates of numerical measures of the defined system functionality threads, which represent the system's operational requirements as specified in the ORD. The tools are directly transferrable and applicable to test and evaluation exercise events which are conducted in support of the development and acquisition of systems and equipment. Once the levels of system performance have been defined, the Paradigm generates a quantitative database that becomes a useful tool in system tradeoffs and selection. Once the alternative system suites have been defined, the suites can be analyzed in terms of system functionality threads and their corresponding performance capabilities versus cost.

关键词： Naval vessels

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Range image registration for free-form surfaces using curvature information as invariance 9

Range image registration for free-form surfaces using curvat...

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9th European Signal Processing Conference, EUSIPCO 1998

作者： Rieder, Markus Guir, Nicolas Dillmann, R. Department for Computer Science Institute for Real-Time Computer Control Systems and Robotics University of Karlsruhe Karlsruhe76128 Germany Department of Computer Architecture University of Malaga Malaga Spain

A curvature based technique for fast range image registration is described in this work. With this technique the rotation and the displacement of a surface with respect to another one is calculated. The proposed algorithm uses Gaussian curvature information from each image point to extract a number of feature points. Two bounds are applied to the curvature values. Points with these bound curvature value are classified into two classes of feature points. In order to calculate the rotation angle between the two range images, the feature points are paired. That means the angle and the distance of the point pairs have to be transformed into a general view coordinate system. In the orientation matching procedure, we compare each pairing in the first image with each possible in the second one. This process is independent of the translation calculation which is calculated in a sequencing step. This pipelining principle speeds up the registration process if correspondences are calculated constantly.

关键词： Image registration

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