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arXiv 2025年

作者： Gu, Jianfeng Wang, Hao Guo, Xiaorang Schulz, Martin Gerndt, Michael Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

As FPGAs gain popularity for on-demand application acceleration in data center computing, dynamic partial reconfiguration (DPR) has become an effective fine-grained sharing technique for FPGA multiplexing. However, current FPGA sharing encounters partial reconfiguration contention and task execution blocking problems introduced by the DPR, which significantly degrade application performance. In this paper, we propose VersaSlot, an efficient spatio-temporal FPGA sharing system with novel *** slot architecture that can effectively resolve the contention and task blocking while improving resource utilization. For the heterogeneous *** architecture, we introduce an efficient slot allocation and scheduling algorithm, along with a seamless cross-board switching and live migration mechanism, to maximize FPGA multiplexing across the cluster. We evaluate the VersaSlot system on an FPGA cluster composed of the latest Xilinx UltraScale+ FPGAs (ZCU216) and compare its performance against four existing scheduling algorithms. The results demonstrate that VersaSlot achieves up to 13.66x lower average response time than the traditional temporal FPGA multiplexing, and up to 2.19x average response time improvement over the state-of-the-art spatio-temporal sharing systems. Furthermore, VersaSlot enhances the LUT and FF resource utilization by 35% and 29% on average, respectively. Copyright © 2025, The Authors. All rights reserved.

关键词： Scheduling algorithms

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KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA

arXiv

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arXiv 2025年

作者： Guo, Xiaorang Bunarjyan, Tigran Liu, Dai Lienhard, Benjamin Schulz, Martin Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany Department of Chemistry Princeton University PrincetonNJ08544 United States Department of Electrical and Computer Engineering Princeton University PrincetonNJ08544 United States

Superconducting qubits are among the most promising candidates for building quantum information processors. Yet, they are often limited by slow and error-prone qubit readout—a critical factor in achieving high-fidelity operations. While current methods, including deep neural networks, enhance readout accuracy, they typically lack support for mid-circuit measurements essential for quantum error correction, and they usually rely on large, resource-intensive network models. This paper presents KLiNQ, a novel qubit readout architecture leveraging lightweight neural networks optimized via knowledge distillation. Our approach achieves around a 99% reduction in model size compared to the baseline while maintaining a qubit-state discrimination accuracy of 91%. KLiNQ facilitates rapid, independent qubit-state readouts that enable mid-circuit measurements by assigning a dedicated, compact neural network for each qubit. Implemented on the Xilinx UltraScale+ FPGA, our design can perform the discrimination within 32 ns. The results demonstrate that compressed neural networks can maintain high-fidelity independent readout while enabling efficient hardware implementation, advancing practical quantum computing. Copyright © 2025, The Authors. All rights reserved.

关键词： Field programmable gate arrays (FPGA)

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Leveraging Hybrid Classical-Quantum Methods for Efficient Load Rebalancing in HPC 24

Leveraging Hybrid Classical-Quantum Methods for Efficient Lo...

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Proceedings of the SC '24 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis

作者： Justyna Zawalska Minh Chung Katarzyna Rycerz Laura Schulz Martin Schulz Dieter Kranzlmüller AGH University of Krakow Institute of Computer Science Krakow Poland and Academic Computer Center CYFRONET AGH Krakow Poland Leibniz Supercomputing Centre (LRZ) Garching bei München Germany and MNM-Team Ludwig-Maximilians-Universität München (LMU) Germany Leibniz Supercomputing Centre (LRZ) Garching bei München Germany Leibniz Supercomputing Centre (LRZ) Garching bei München Germany and Chair for Computer Architecture and Parallel Systems Technical University of Munich (TUM) Germany

ISBN: (纸本)9798350355543

Load imbalance is a challenge for parallel applications in High Performance Computing (HPC). It is caused by processes having different execution times or load values, leading to idle or wait times at synchronization points, where faster processes must wait for the slowest process to catch up. To mitigate this issue, applications can employ load balancing (LB) strategies, which migrate load between processes to even out load. This is often referred to as the Load Rebalancing Problem (LRP). While many approaches solving the LRP exist, they can only be heuristics and hence further optimization potential exists. In our work, we turn to a novel approach by using hybrid classical-quantum approaches and present two versions of the constrained quadratic model for solving the LRP; the two differ in how they balance the number of qubits required with the types of applied constraints. We compare the quantum-based methods with classical methods using heuristic algorithms Greedy, Karmarkar--Karp, and ProactLB. We evaluate our approaches using imbalance ratio and speedup as metrics, as well as the number of migrated tasks to indicate overhead caused by migrations. Our results show that the quantum-based methods outperform the classic methods. For example, we need only 1/4 of the number of migrated tasks in a realistic use case compared with classical methods, particularly Greedy and KK, to balance the load.

关键词： CQM

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Leveraging Hybrid Classical-Quantum Methods for Efficient Load Rebalancing in HPC

Leveraging Hybrid Classical-Quantum Methods for Efficient Lo...

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2024 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC Workshops 2024

作者： Zawalska, Justyna Chung, Minh Rycerz, Katarzyna Schulz, Laura Schulz, Martin Kranzlmuller, Dieter AGH University of Krakow Institute of Computer Science Krakow Poland CYFRONET AGH Academic Computer Center Krakow Poland Garching bei München Germany Chair for Computer Architecture and Parallel Systems Germany MNM-Team Germany

ISBN: (纸本)9798350355543

Load imbalance is a challenge for parallel applications in High Performance Computing (HPC). It is caused by processes having different execution times or load values, leading to idle or wait times at synchronization points, where faster processes must wait for the slowest process to catch up. To mitigate this issue, applications can employ load balancing (LB) strategies, which migrate load between processes to even out load. This is often referred to as the Load Rebalancing Problem (LRP). While many approaches solving the LRP exist, they can only be heuristics and hence further optimization potential exists. In our work, we turn to a novel approach by using hybrid classical-quantum approaches and present two versions of the constrained quadratic model for solving the LRP;the two differ in how they balance the number of qubits required with the types of applied constraints. We compare the quantum-based methods with classical methods using heuristic algorithms Greedy, Karmarkar-Karp, and ProactLB. We evaluate our approaches using imbalance ratio and speedup as metrics, as well as the number of migrated tasks to indicate overhead caused by migrations. Our results show that the quantum-based methods outperform the classic methods. For example, we need only 1/4 of the number of migrated tasks in a realistic use case compared with classical methods, particularly Greedy and KK, to balance the load. © 2024 IEEE.

关键词： CQM HPC HPCQC integration Load Rebalancing Quantum Computing task migration

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Integration of Quantum Accelerators into HPC: Toward a Unified Quantum Platform

arXiv

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arXiv 2024年

作者： Elsharkawy, Amr Guo, Xiaorang Schulz, Martin Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale superlinearly with number of qubits, which is critical to support scalability efforts in QC hardware. Copyright © 2024, The Authors. All rights reserved.

关键词： Trapped ions

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Integration of Quantum Accelerators into HPC: Toward a Unified Quantum Platform

Integration of Quantum Accelerators into HPC: Toward a Unifi...

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Quantum Computing and Engineering (QCE), IEEE International Conference on

作者： Amr Elsharkawy Xiaorang Guo Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

ISBN: (数字)9798331541378

ISBN: (纸本)9798331541385

To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale super-linearly with number of qubits, which is critical to support scalability efforts in OC hardware.

关键词： Runtime library Scalability High performance computing Qubit Process control Atoms Hardware Software Performance analysis Logic

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A Scalable and Cross-Technology Quantum Control Processor

A Scalable and Cross-Technology Quantum Control Processor

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International Conference on Field Programmable Logic and Applications

作者： Xiaorang Guo Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany

Quantum control processors (QCPs) bridge the gap between the quantum software and the hardware backend to construct full-stack quantum computers. In this study, the quantum backend interface is responsible for generating pulses to control qubits, where commercial waveform generators or specific converters are typically needed. A radio frequency system-on-chip (RFSoC)-based QCP supports a direct control pulse synthesis without additional components. Therefore, in this work, we propose an RFSoC-based QCP that integrates the processor and pulse generation logic onto a single board. With the help of the proposed instruction set and efficient microarchitecture implementation, the QCP offers large scalability for controllable qubits, while supporting different physical platforms.

关键词：

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iCheck: Leveraging RDMA and Malleability for Application-Level Checkpointing in HPC systems

iCheck: Leveraging RDMA and Malleability for Application-Lev...

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International Conference on parallel and Distributed systems (ICPADS)

作者： Jophin John Isaac David Núñez Araya Michael Gerndt Chair of Computer Architecture and Parallel Systems Technische Universität München Germany

The estimate that the mean time between failures will be in minutes in exascale supercomputers should be alarming for application developers. The inherent system’s complexity, millions of components, and susceptibility to failures make checkpointing more relevant than ever. Since most high performance scientific applications contain an in-house checkpoint restart mechanism, their performance can be impacted by the contention of parallel file system resources. A shift in checkpointing strategies is needed to thwart this behavior. With iCheck, we present a novel checkpointing framework that supports malleable multilevel application-level checkpointing. We employ an RDMA enabled configurable multi-agent-based checkpoint transfer mechanism where minimal application resources are utilized for checkpointing. The high-level API of iCheck facilitates easy integration and malleability. We have added the iCheck library into the Is1 mardyn application providing performance improvement up to five thousand times over the in-house checkpointing mechanism. LULESH, Jacobi 2D heat simulation, and a synthetic application were also used for extensive analysis.

关键词： Checkpointing Jacobian matrices Heating systems Fault tolerance File systems Fault tolerant systems Supercomputers

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IaaS Reactive Autoscaling Performance Challenges

IaaS Reactive Autoscaling Performance Challenges

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IEEE International Conference on Cloud Computing, CLOUD

作者： Vladimir Podolskiy Anshul Jindal Michael Gerndt Chair for Computer Architecture and Parallel Systems Technical University of Munich Garching (near Munich) Germany

The main feature of a cloud application is its scalability. Major IaaS cloud services providers (CSP) employ autoscaling on the level of virtual machines (VM). Other virtualization solutions (e.g. containers, pods) can also scale. An application scales in response to change in observed metrics, e.g. in CPU utilization. Occasionally, cloud applications exhibit the inability to meet the Quality of Service (QoS) requirements during the scaling caused by the reactivity of autoscaling solutions. This paper provides the results of the autoscaling performance evaluation for two-layered virtualization (VMs and Kubernetes pods) conducted in the public clouds of AWS, Microsoft and Google using the approach and the Autoscaling Performance Measurement Tool developed by the authors.

关键词： Cloud computing Quality of service Measurement Virtualization Google Tools Scalability

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An Accurate and Hardware-Efficient Dual Spike Detector for Implantable Neural Interfaces

An Accurate and Hardware-Efficient Dual Spike Detector for I...

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2022 IEEE Biomedical Circuits and systems Conference, BioCAS 2022

作者： Guo, Xiaorang Shaeri, MohammadAli Shoaran, Mahsa Institute of Electrical and Micro Engineering Center for Neuroprosthetics Epfl Geneva1202 Switzerland Faculty of Electrical and Computer Engineering Technische Universität Dresden Dresden01069 Germany Chair of Computer Architecture and Parallel Systems Technische Universität München Garching85748 Germany

ISBN: (数字)9781665469173

ISBN: (纸本)9781665469173

Spike detection plays a central role in neural data processing and brain-machine interfaces (BMIs). A challenge for future-generation implantable BMIs is to build a spike detector that features both low hardware cost and high performance. In this work, we propose a novel hardware-efficient and high-performance spike detector for implantable BMIs. The proposed design is based on a dual-detector architecture with adaptive threshold estimation. The dual-detector comprises two separate TEO-based detectors that distinguish a spike occurrence based on its discriminating features in both high and low noise scenarios. We evaluated the proposed spike detection algorithm on the Wave Clus dataset. It achieved an average detection accuracy of 98.9%, and over 95% in high-noise scenarios, ensuring the reliability of our method. When realized in hardware with a sampling rate of 16kHz and 7-bits resolution, the detection accuracy is 97.4%. Designed in 65nm TSMC process, a 256-channel detector based on this architecture occupies only 682μm2/Channel and consumes 0.07μW/Channel, improving over the state-of-the-art spike detectors by 39.7% in power consumption and 78.8% in area, while maintaining a high accuracy. © 2022 IEEE.

关键词： Data handling

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