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IEEE International SOC Conference

作者： Shuang Liu Martin Radetzki Chair of Embedded Systems Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany

ISBN: (数字)9798350377569

ISBN: (纸本)9798350377576

Chiplet-based systems have become prominent in large systems-on-Chips (SoCs) as a means to mitigate increasing design costs. However, the integration of multiple chiplets introduces new challenges in the interconnection network, potentially leading to deadlocks. In this paper, we propose an Integer Linear Programming (ILP) based design approach to address this issue. Our method considers various design factors for deadlock-free routing, such as topology, latency, load balancing, path diversity, and fault tolerance, applicable to both general-purpose chiplets and application-specific chiplets. It facilitates the determination of optimal turn restrictions for general-purpose chiplets or constructs optimal deadlock-free routing paths for application-specific chiplets if the communication patterns are known. The results demonstrate the capability of the method to find optimal solutions under various design considerations.

关键词： Fault tolerance Network topology Chiplets Fault tolerant systems System recovery Integer linear programming Routing Load management Topology System-on-chip

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Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming

Systematic Construction of Deadlock-Free Routing for NoC Usi...

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IEEE International Symposium on embedded Multicore Socs (MCSoC)

作者： Shuang Liu Martin Radetzki Chair of Embedded Systems Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany

Network-on-Chip (NoC) presents a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs). This work addresses critical challenges in NoC design, including routing construction, application mapping, and particularly the issue of deadlocks in the widely-used wormhole routing method. In this paper, an Integer Linear Programming (ILP) approach for deadlock-free routing is proposed, applicable to arbitrary network topologies. We systematically analyze deadlock-free routing construction for mesh and torus topologies under uniform random traffic and provide alternative solutions to turn models. In the context of application-specific NoCs, application mapping, and deadlock-free routing are integrated within a single ILP. Through evaluation with several benchmark applications, it is demonstrated that the ILP method consistently delivers optimal solutions and could obtain better results than various heuristic methods within an acceptable time. Fault tolerance is also explored and existing techniques are incorporated into the ILP approach. As an illustrative example, application mapping and a 1-link-fault-tolerant deadlock-free routing for the MP3 application on a mesh network is performed.

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Synergistic Floorplanning and Routing Topology Co-design for Application-Specific NoC Synthesis

Synergistic Floorplanning and Routing Topology Co-design for...

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IEEE International Symposium on embedded Multicore Socs (MCSoC)

作者： Shuang Liu Martin Radetzki Chair of Embedded Systems Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

Network-on-Chip (NoC) offers a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs). NoCs can be designed with either regular or application-specific network topologies. While regular topologies are easy to design, they are not ideal for systems with heterogeneous processing elements (PEs) that vary in size. The design of application-specific NoCs, however, involves several interrelated problems that impact each other. This work addresses the challenges in the synthesis of application-specific NoCs by proposing an Integer Linear Programming (ILP) framework. This framework enables the co-design of major problems, including floorplanning, routing topology generation, routing path construction, and application mapping. Although the ILP framework can be applied to each problem individually or in a stepwise manner, the co-design of these interconnected problems allows synthesis steps to interact, enabling designers to explore the entire design space. Using this framework, we have analyzed various design configurations in the synthesis of application-specific NoCs.

关键词： Network topology Multicore processing Fault tolerant systems Network-on-chip System recovery Integer linear programming Routing Linear programming Topology Wire

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MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing

MEPNTC: A Standard-Cell Library Design Scheme Extending the ...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Anuradha C. Ranasinghe Sabih H. Gerez Chair of Computer Architecture for Embedded Systems Faculty of Electrical Engineering University of Twente Enschede Netherlands

ISBN: (数字)9781728197104

ISBN: (纸本)9781728197111

This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- V th operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- V th level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.

关键词： Transform coding CMOS technology Libraries Hardware Energy efficiency Standards Resilience

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Transparent structural online test for reconfigurable systems

Transparent structural online test for reconfigurable system...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Mohamed S. Abdelfattah Lars Bauer Claus Braun Michael E. Imhof Michael A. Kochte Hongyan Zhang Jörg Henkel Hans-Joachim Wunderlich Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany Chair for Embedded Systems Karlsruhe Institute of Technology Germany

FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

关键词： Containers Field programmable gate arrays Testing Table lookup Runtime Random access memory Fabrics

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Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures

Module diversification: Fault tolerance and aging mitigation...

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IEEE International Test Conference

作者： Hongyan Zhang Lars Bauer Michael A. Kochte Eric Schneider Claus Braun Michael E. Imhof Hans-Joachim Wunderlich Jörg Henkel Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany

ISBN: (纸本)9781479908608

Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.

关键词： Stress Circuit faults Aging Runtime Field programmable gate arrays Containers Reliability

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STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures 15

STRAP: Stress-aware placement for aging mitigation in runtim...

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IEEE International Conference on computer-Aided Design

作者： Hongyan Zhang Michael A. Kochte Eric Schneider Lars Bauer Hans-Joachim Wunderlich Jörg Henkel Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany

ISBN: (纸本)9781467383899

Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured in the latest technology node, aging is amajor concern. We introduce the first cross-layer aging-aware placement method for accelerators in FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator placement at runtime, i.e. to which reconfigurable region an accelerator shall be reconfigured. Additionally, it optimizes logic placement at synthesis time to diversify the resource usage of individual accelerators, i.e. which CLBs of a reconfigurable region shall be used by an accelerator. Both layers together balance the intra- and inter-region stress induced by the application workload at negligible performance cost. Experimental results show significant reduction of maximum stress of up to 64% and 35%, which leads to up to 177% and 14% MTTF improvement relative to state-of-the-art methods w.r.t. HCI and BTI aging, respectively.

关键词： Stress Runtime Aging Transistors Table lookup Fabrics Field programmable gate arrays

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Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing

Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Anuradha C. Ranasinghe Sabih H. Gerez Chair of Computer Architecture for Embedded Systems Faculty of Electrical Engineering University of Twente 5 Drienerlolaan 7522 NB Enschede Netherlands

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper presents two novel circuit arrangements for an ultra-low voltage, low-power 4-to-2 compressor targeting typical near-V th application domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4V DD compared to most appealing implementations in literature.

关键词： Transistors Compressors Delays Adders Logic gates Synchronization Inverters

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Accurate ICP-based floating-point reasoning 16

Accurate ICP-based floating-point reasoning

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Formal Methods in computer Aided Design (FMCAD)

作者： Karsten Scheibler Felix Neubauer Ahmed Mahdi Martin Fränzle Tino Teige Tom Bienmüller Detlef Fehrer Bernd Becker Chair of Computer Architecture University of Freiburg Germany Research Group Hybrid Systems Carl von Ossietzky University of Oldenburg Germany BTC Embedded Systems AG Oldenburg Germany Sick AG Waldkirch Germany

ISBN: (纸本)9780983567868

In scientific and technical software, floating-point arithmetic is often used to approximate arithmetic on physical quantities natively modeled as reals. Checking properties for such programs (e.g. proving unreachability of code fragments) requires accurate reasoning over floating-point arithmetic. Currently, most of the SMT-solvers addressing this problem class rely on bit-blasting. Recently, methods based on reasoning in interval lattices have been lifted from the reals (where they traditionally have been successful) to the floating-point numbers. The approach presented in this paper follows the latter line of interval-based reasoning, but extends it by including bitwise integer operations and cast operations between integer and floating-point arithmetic. Such operations have hitherto been omitted, as they tend to define sets not concisely representable in interval lattices, and were consequently considered the domain of bit-blasting approaches. By adding them to interval-based reasoning, the full range of basic data types and operations of C programs is supported. Furthermore, we propose techniques in order to mitigate the problem of aliasing during interval reasoning. The experimental results confirm the efficacy of the proposed techniques. Our approach outperforms solvers relying on bit-blasting as well as the existing interval-based SMT-solver.

关键词： Cognition Lattices Iterative closest point algorithm Open area test sites Context Computational modeling Encoding

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Self-Awareness for Autonomous systems

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PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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