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On Strong Secrecy for Multiple Access Channels With States and Causal CSI

IEEE Transactions on Information Theory 2025年第4期71卷 3070-3099页

作者： Chen, Yiqi Oechtering, Tobias J. Skoglund, Mikael Luo, Yuan Technical University of Munich Chair of Theoretical Information Technology Munich80333 Germany Shanghai Jiao Tong University Department of Computer Science and Engineering Shanghai200240 China KTH Royal Institute of Technology Division of Information Science and Engineering School of Electrical Engineering and Computer Science Stockholm100 44 Sweden Shanghai Key Laboratory of Trusted Data Circulation and Governance and Web3 Shanghai200240 China

Strong secrecy communication over a discrete memoryless state-dependent multiple access channel (SD-MAC) with an external eavesdropper is investigated. The channel is governed by discrete memoryless and i.i.d. channel states, and the channel state information (CSI) is revealed to the encoders in a causal manner. The main results of this paper are inner and outer bounds of the capacity region, for which we investigate coding schemes incorporating wiretap coding and secret key agreements between the sender and the legitimate receiver. Two kinds of block Markov coding schemes are proposed. The first is a new coding scheme that uses backward decoding and the Wyner-Ziv coding, and the secret key is constructed from a lossy description of the CSI. The other is an extended version of an existing coding scheme for point-to-point wiretap channels with causal CSI. A numerical example shows that the achievable region given by the first coding scheme can be strictly larger than the second one. However, these two schemes do not outperform each other in general, and there exist some numerical examples in which each coding scheme achieves some rate pairs that cannot be achieved by another scheme. Our established inner bound reduces to some best-known results in the literature as special cases. We further investigate some capacity-achieving cases for state-dependent multiple access wiretap channels (SD-MAWCs) with degraded message sets. It turns out that the two coding schemes are both optimal in these cases. © 1963-2012 IEEE.

关键词： Markov processes

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Enhancing LLM Code Generation Using Natural Language Processing in the Context of Machine Learning 28th

Enhancing LLM Code Generation Using Natural Language Process...

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28th International Symposium on Database Engineered Applications, IDEAS 2024

作者： Nelson, Jordan Pavlidis, Michalis Fish, Andrew Polatidis, Nikolaos School of Architecture Technology and Engineering University of Brighton BrightonBN2 4GJ United Kingdom Department of Computer Science University of Liverpool LiverpoolL69 3BX United Kingdom

ISBN: (纸本)9783031834714

The rapid rise in popularity of Generative AI and Large Language Models (LLMs) has brought both innovation and controversy, particularly regarding plagiarism and IP law infringements. However, one underexplored concern is the generation of code by these models, which, despite their potential, often includes errors and promotes poor programming practices. This paper explores new methods to address these issues by integrating LLMs with Automated Machine Learning (AutoML). By leveraging AutoML’s capabilities in hyperparameter tuning and model selection, we propose a novel approach for generating robust machine learning algorithms. This integration aims to enhance the accuracy and reliability of code generation while mitigating legal risks. Our findings include the application of Natural Language Processing (NLP) and Natural Language Understanding (NLU) techniques to interpret chatbot prompts, thereby improving the generation and customization of machine learning models. The proposed methodology demonstrates practical implementation and high prediction accuracy, offering a promising solution to the current challenges faced by LLM-based code generation. In summary the findings of the paper are as follows: A new implementation of natural language processing for natural language understanding in the context of chatbot prompts aims to serve as an initial step for feature extraction, which will be utilised by an AutoML system to generate machine learning algorithms. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Adversarial machine learning

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Technical Language Processing for Telecommunications Specifications

Applied AI Letters

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Applied AI Letters 2025年第2期6卷

作者： Rodriguez Y, Felipe A. L3 Architecture and Specification Nokia Networks Oy Uusimaa Finland Department of Computer Science Aalto University Uusimaa Finland

Large Language Models (LLMs) are continuously being evaluated in more diverse contexts. However, they still have challenges when extracting information from highly specific internal technical documentation. One specific area of real-world technical documentation is telecommunications engineering, which could benefit from domain-specific LLMs. In this article, we expand the notion of Technical Language Processing (TLP) to the telecommunications domain by introducing and analyzing the format of technical specifications from a leading telecommunications equipment vendor. Additionally, we highlight the importance of use case definitions by introducing requirement property mapping for maximizing information extraction. Also, we recommend actions to mitigate the effect of the internal specifications format on information extraction, which can lead to LLM-friendly internal specifications. Finally, a PoC is built to showcase the improvements of our proposed framework. © 2025 The Author(s). Applied AI Letters published by John Wiley & Sons Ltd.

关键词： NLP technical specification telecommunications TLP

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Leveraging Hybrid Classical-Quantum Methods for Efficient Load Rebalancing in HPC 24

Leveraging Hybrid Classical-Quantum Methods for Efficient Lo...

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Proceedings of the SC '24 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis

作者： Justyna Zawalska Minh Chung Katarzyna Rycerz Laura Schulz Martin Schulz Dieter Kranzlmüller AGH University of Krakow Institute of Computer Science Krakow Poland and Academic Computer Center CYFRONET AGH Krakow Poland Leibniz Supercomputing Centre (LRZ) Garching bei München Germany and MNM-Team Ludwig-Maximilians-Universität München (LMU) Germany Leibniz Supercomputing Centre (LRZ) Garching bei München Germany Leibniz Supercomputing Centre (LRZ) Garching bei München Germany and Chair for Computer Architecture and Parallel Systems Technical University of Munich (TUM) Germany

ISBN: (纸本)9798350355543

Load imbalance is a challenge for parallel applications in High Performance Computing (HPC). It is caused by processes having different execution times or load values, leading to idle or wait times at synchronization points, where faster processes must wait for the slowest process to catch up. To mitigate this issue, applications can employ load balancing (LB) strategies, which migrate load between processes to even out load. This is often referred to as the Load Rebalancing Problem (LRP). While many approaches solving the LRP exist, they can only be heuristics and hence further optimization potential exists. In our work, we turn to a novel approach by using hybrid classical-quantum approaches and present two versions of the constrained quadratic model for solving the LRP; the two differ in how they balance the number of qubits required with the types of applied constraints. We compare the quantum-based methods with classical methods using heuristic algorithms Greedy, Karmarkar--Karp, and ProactLB. We evaluate our approaches using imbalance ratio and speedup as metrics, as well as the number of migrated tasks to indicate overhead caused by migrations. Our results show that the quantum-based methods outperform the classic methods. For example, we need only 1/4 of the number of migrated tasks in a realistic use case compared with classical methods, particularly Greedy and KK, to balance the load.

关键词： CQM

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A SystemC Based Framework for Cycle Accurate Processor Simulation and Parameter Analysis

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IFAC-PapersOnLine 2016年第25期49卷 92-97页

作者： Kohl, Johannes Reichenbach, Marc Demel, Carsten Fey, Dietmar Department of Computer Science Chair of Computer Architecture Friedrich-Alexander-University Erlangen-Nuremberg Germany

The development of new domain specific microprocessors architectures is a very complex task. Hardware designers are confronted with several hundred design parameters (e.g. cache size, ALU operation, etc.) which can be combined in a nearly arbitrary way to develop new architectures. Often these parameters are guessed by the designer or best practice is used to find an apparently good parameter set. The utilization of virtual hardware can be one solution to solve this problem. Different parameter sets can be evaluated inside a simulation environment, without the need for designing any real hardware. Unfortunately, most virtual hardware simulators are either to inflexible or not accurate enough to get valuable results. Therefore, this paper presents a SystemC based framework, which enables the construction of highly parameterizable virtual hardware processor models, directed at parameter analysis. The structure and working principle of two exemplary processors are showcasing the use of this framework. A presentation of how different parameter sets impact the programs execution time and power consumption of the processor will be given, as a result of the virtual hardwares execution. © 2016

关键词： Integrated circuit design Application programs Hardware Simulators Cycle accurate Design space exploration Design tool Emulators Microprocessor based control

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Plausibility in Early Stages of Architectural Design: A New Tool for High-Rise Residential Buildings

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Tsinghua science and Technology 2009年第3期14卷 327-332页

作者： Dirk Donath Danny Lobos Chair of Computer Science in Architecture Faculty of Architecture Bauhaus-UniversityWeimar 99423 Germany

This paper analyzes the problem of the design of envelopes for high-rise isolated residential buildings. The phenomenon of envelope creation appears in the early stages of the architectural design. Variables that influence the final shape and size of such envelopes are then identified. This paper presents the state-of-the-art tools for the current solutions at the commercial and academic/scientific level. The variables identified in this research are the client＇s needs, the urban code and architectural practice, and their specific components for the final creation of a new decision support system tool based on the building information modeling （BIM） software platform, to facilitate the work in the project development and drawing production stages. This tool generates several options for building envelopes according to the parameters required by the city Zoning Planning Commission. These options then lead to deliver reliable data and a geometry that can be analyzed in a timely fashion by the engineers, builders, architects, government, and clients in the early stages of the building＇s design. The results show that use of specific information and communication technologies （ICT） tools in the early stages of a building design helps reduce the working time, increases confidence in the generated solution, and contributes to the exploration of alternatives in a short period of time.

关键词： constraint based design parametric programming urban modeling optimization architectural design

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Intelligent Interactive Assistance and Mobile Multimedia Computing 1

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丛书名： Communications in computer and Information science

1000年

作者： Djamshid Tavangarian Thomas Kirste Dirk Timmermann Ulrike Lucke Daniel Versick

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Fe2vCl2 - From bare metal to high performance computing on virtual clusters and cloud infrastructure 4

Fe2vCl2 - From bare metal to high performance computing on v...

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4th Workshop on CrossCloud Infrastructures and Platforms, CrossCloud 2017

作者： DItter, Alexander Graf, Gabriel Fey, DIetmar Department of Computer Science Computer Architecture Martensstr. 3 Erlangen91058 Germany

ISBN: (纸本)9781450349345

Container based virtualization techniques are playing a more and more important role in cloud and service oriented computing. Technologies, such as Docker, enable the development and deployment of new and especially light weight applications and allow for a more cloud provider independent operation. Even though cloud infrastructure and containers offer many advantages, both technologies have yet to be widely utilized in the field of High Performance Computing. In this paper we present Fe2vCl2, a framework for enabling HPC applications on common cloud infrastructure. Using Docker to integrate it into cloud environments, our framework allows the on-demand deployment of virtual clusters for the parallel execution of HPC applications. We describe our overall application architecture along with the advantages of both technologies, especially with regard to HPC applications. In order to verify our implementation we evaluate it using different HPC applications and benchmarks. Copyright © 2017 ACM.

关键词： Containers

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The smart miniFab: An industrial IoT demonstrator anywhere at any time 4th

The smart miniFab: An industrial IoT demonstrator anywhere a...

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4th International KES conference on Smart Education and Smart e-Learning, SEEL 2017

作者： Schubert, Tobias Völker, Benjamin Pfeifer, Marc Becker, Bernd Chair of Computer Architecture Faculty of Engineering Institute of Computer Science Albert-Ludwigs-University Freiburg Freiburg79110 Germany

ISBN: (纸本)9783319594507

The fourth industrial revolution is predicted to be one major topic in the upcoming decades, affecting nearly every industrial facility. The key enabler for the successful integration of corresponding developments are well-trained engineers with elaborated knowledge in the area of the Industrial Internet of Things (IIoT). This paper introduces a concept enabling engineering students to gain the required skills for the upcoming challenges connected with the fourth industrial revolution. Therefore, the Smart MiniFab was developed - a demonstrator of an industrial facility primed for the implementation and the analysis of different IIoT concepts on a small scale. Due to the modular structure of the system, students can use the demonstrator to programmatically implement the functionality of an entire facility from scratch or to test only certain new concepts. The hardware can be programmed via remote access from anywhere at any time, while live feedback is provided through a webcam and different other communication possibilities directly within the remote access application. While the Smart MiniFab was already the HW environment of different student projects, a new lab course is currently under development which enables the access to the Smart MiniFab for a broad number of students. © Springer International Publishing AG 2018.

关键词： Students

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Efficient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers

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Journal of computer science & Technology 2012年第1期27卷 75-91页

作者： Benjamín Sahelices Agustín de Dios Pablo Ibáez Víctor Vials-Yúfera José María Llabería Computer Science Department and HiPEAC European Network of Excellence University of Valladolid Valladolid Spain Computer Science and Systems Engineering Department I3A Research Institute and HiPEAC European Network of Excellence University of Zaragoza Zaragoza Spain Computer Architecture Department and HiPEAC European Network of Excellence Polytechnic University of Catalua Barcelona Spain

Synchronization in parallel programs is a major performance bottleneck in multiprocessor systems. Shared data is protected by locks and a lot of time is spent on the competition arising at the lock hand-off. In order to be serialized, requests to the same cache line can either be bounced （NACKed） or buffered in the coherence controller. In this paper, we focus mainly on systems whose coherence controllers buffer requests. In a lock hand-off, a burst of requests to the same line arrive at the coherence controller. During lock hand-off only the requests from the winning processor contribute to progress of the computation, since the winning processor is the only one that will advance the work. This key observation leads us to propose a hardware mechanism we call request bypassing, which allows requests from the winning processor to bypass the requests buffered in the coherence controller keeping the lock line. We present an inexpensive implementation of request bypassing that reduces the time spent on all the execution phases of a critical section （acquiring the lock, accessing shared data, and releasing the lock） and which, as a consequence, speeds up the whole parallel computation. This mechanism requires neither compiler or programmer support nor ISA or coherence protocol changes. By simulating a 32-processor system, we show that using request bypassing does not degrade but rather improves performance in three applications with low synchronization rates, while in those having a large amount of synchronization activity （the remaining four）, we see reductions in execution time and in lock stall time ranging from 14% to 39% and from 52% to 7170, respectively. We compare request bypassing with a previously proposed technique called read combining and with a system that bounces requests, observing a significantly lower execution time with the bypassing scheme. Finally, we analyze the sensitivity of our results to some key hardware and software parameters.

关键词： distributed shared memory multiprocessors synchronization buffer coherence controller request bypass

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