检索结果-内蒙古大学图书馆

2001 IEEE International Conference on Cluster Computing, CLUSTER 2001

作者： Seifert, Friedrich Rehm, Wolfgang Chemnitz University of Technology Department of Computer Science Chair of Computer Architecture Strabe der Nationen 62 Chemnitz09111 Germany

ISBN: (纸本)0769511163

A major trend in recent cluster communication systems is to circumvent the operating system during the actual data transfers. That, on the one hand, reduces latency since there is no user-kernel transition needed and, on the other hand, increases bandwidth by avoiding additional intermediate copies. The data transfer is handled completely by the networking hardware and its DMA engine. For example, the Virtual Interface processes can access networking hardware directly in a protected manner. One of its characteristics is that it requires that all memory used for communication be locked down into physical memory. The same requirement holds true for the Infiniband ensures reliable locking of regular, i.e. private, virtual memory without altering the kernel. In this paper we present an extended solution that can handle System V shared memory as well. © 2001 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： Linux

来源：评论

学校读者我要写书评

暂无评论

IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures

IPAS: a design framework for analysis, synthesis and optimiz...

引用

作者： Hartmann, C. Häublein, K. Reichenbach, M. Fey, D. Chair of Computer Architecture University of Erlangen-Nuremberg Martensstr. 3 Erlangen91058 Germany

Recent trends in the image processing field have led to the use of more heterogeneous hardware architectures. The reason for this increase is that specialized cores, compared to standard CPUs, offer a more efficient way of achieving image processing applications. Specialized cores have less power, resource, and area consumption. On the other hand, designing such a heterogenous system with specialized cores is a challenging, error-prone and time-consuming task. Therefore, new frameworks are necessary for bringing an image processing application onto a given target platform by means of a tool chain. Some frameworks exist, but they do not address each need of a heterogeneous image processing application. Common weaknesses are (1) the low utilization of the image processing domain, (2) the inflexibility of the programming paradigms for different hardware architectures. Therefore, we define our own domain-specific design language called IPOL. To automate the derivation and optimization process, a synthesis tool named Image Processing architecture Synthesis was created. This tool will be the focus of this work. © 2016, Springer-Verlag Berlin Heidelberg.

关键词： Program processors

来源：评论

学校读者我要写书评

暂无评论

An extended analysis of memory hierarchies for efficient implementations of image processing applications

An extended analysis of memory hierarchies for efficient imp...

引用

作者： Hartmann, Christian Fey, Dietmar Chair of Computer Architecture University of Erlangen-Nuremberg Martensstr. 3 Erlangen91058 Germany

Through continued miniaturization of electronic devices embedded smart cameras are steadily becoming more and more important. The reduction of the camera size increases the spectrum of applications. In industrial applications the range of smart cameras spans from quality monitoring and position tracking to the calibration of production machines. In non-professional applications a distinct boom in action cameras combined with fused sensor information can be observed. However, all of these applications have a common bottleneck: the memory architecture. Most image processing applications are memory-bound tasks. Thus, the amount of time for transferring data with image processing applications decisively affects the application’s entire processing time. Different memory access patterns require different memory configurations and hierarchies. An insufficient match between the image processing application and the memory architecture leads to a poor performance in the image processing system. This can lead to longer processing times, and larger energy consumption rates. This work introduces new methods of classifying image processing applications by using their memory access pattern for mapping on memory architectures. Our work combines a simulation framework the heterogenous memory simulator with a analytical framework the memory analyzer to find bottlenecks inside the image processing application and aids in finding a suitable, application-specific memory configuration in terms of processing time and energy consumption. © 2017, Springer-Verlag GmbH Germany.

关键词： Memory architecture

来源：评论

学校读者我要写书评

暂无评论

An annotation tool for enhancing the user interface generation process for services

An annotation tool for enhancing the user interface generati...

引用

KpbiMuKo 2009 CriMiCo - 2009 19th International Crimean Conference Microwave and Telecommunication Technology

作者： Izquierdo, Paoli Janeiro, Jordan Hübsch, Gerald Springer, Thomas Schill, Alexander Department of Computer Science Institute of System Architecture Chair of Computer Networks Dresden Technical University Dresden Sachsen 01187 Germany

ISBN: (纸本)9789663352497

The user interface generation process is still a complex issue. The manual creation process is time consuming and complex because it requires the combination of the application developer work and the user interface designer work. Therefore, many approaches investigate the automatic user interface generation. However, currently such approaches are not able to take usability aspects into account, due to the lack of information for such a process. Thus, we propose a tool which intends to ease and enhance the automatic user interface generation process for services by introducing service annotations that are attached to services and provide additional information for the process of automatic user interface generation. © 2009: CriMiCo'2009 Organizing Committee.

关键词：

来源：评论

学校读者我要写书评

暂无评论

The AllScale runtime interface - Theoretical foundation and concept 9

The AllScale runtime interface - Theoretical foundation and ...

引用

9th Workshop on Many-Task Computing on Clouds, Grids, and Supercomputers, MTAGS 2016

作者： Hendricks, Arne Heller, Thomas Jordan, Herbert Thoman, Peter Fahringer, Thomas Fey, Dietmar Department of Computer Science 3 Computer Architecture Friedrich Alexander University Erlangen Erlangen Germany Institute of Computer Science University of Innsbruck Innsbruck Austria

ISBN: (纸本)9781509052127

Extreme scale HPC systems are expected to reach exascale performance around the year 2020. While it is widely known that theses systems pose new challenges regarding energy efficiency of architectures, concurrency and resiliency, they also challenge developers of applications trying to efficiently utilizing resources: Managing parallel control flows, hardware resources and dependencies is a complex and labor-intensive endeavor. We present here the concept of a runtime interface for the AllScale environment, a novel and sophisticated approach to the decoupling of specification of parallelism from underlying management activities during runtime. AllScale itself utilizes a parallel programming model based on nested recursive parallelism as foundation to add compiler and runtime based techniques to harness performance gains of modern architectures. Automated Porting to extreme scale architectures, flexible tuning and hardware management are only among the things that will be additionally added. One core component of the system will consequently be the runtime with its interface to the other components. In this paper we will present our concept of a runtime interface, based on a theoretical foundation influenced by the tuple-space paradigm. The tuple-space will be augmented by asynchronous computation together with fine grained synchronization based on futures resembling the recursive control flow adding both decomposability as well as set-like behavior to the notion of a tuple. © 2016 IEEE.

关键词： Energy efficiency

来源：评论

学校读者我要写书评

暂无评论

Modelling of aircraft trajectories for emergency landing using kinematoid chains

引用

CEAS Aeronautical Journal 2023年第3期14卷 679-692页

作者： Flämig, Steffen Graefenhan, Matthias Schiffmann, Wolfram FernUniversität in Hagen Chair of Computer Architecture Universitätsstraße 47 Hagen58097 Germany Department of Mathematics and Computer Science Philipps-Universität Marburg Hans-Meerwein-Straße 6 Marburg35032 Germany

Most methods that compute trajectories for un- or low-powered flight operate under simplifying assumptions such as constant curve radii and wind conditions. Likewise, changes of air density with altitude that lead to significant differences between equivalent airspeed (EAS) und true airspeed (TAS) are often not considered. Some approaches are based on Dubins paths, which are introduced in Dubins LE (Am J Math 79: 497, 1957). They combine three sections to form a trajectory, which is the shortest from a given start to an end position (In the original work, the position extended by the heading, is referred to as configuration. Since configuration has a different connotation in our context, we use the term state, which can contain other parameters in addition to the position and the heading, e.g. orientation, configuration of landing flaps, landing gear, etc.). A maximum distant landing spot can be reached this way. Often, the targeted landing spot is closer to the aircraft. If it is approached using a Dubins Path, the excess height must be dealt with. Here, we present a method addressing the problem directly, namely finding a trajectory which reduces the excess height over its entire length. Furthermore, it takes spatial and temporal changes of wind and air density into account. Several conditions influence the final shape of the trajectory. For example, avoidance of obstacles and predefined areas is easily achieved. Our method is motivated by kinematic chains, which are used in robotics and computer animation. We extend and modify this principle by incrementally transferring start and end states of the trajectory, modelled as state vectors, into each other. The resulting intermediate states form ends of chain links. To connect initial and final states through the resulting chain, we solve the inverse kinematic problem known from robotics. We extend it by several conditions, which are derived from the flight mechanical characteristics of the modeled aircraft on the on

关键词： Inverse problems

来源：评论

学校读者我要写书评

暂无评论

Linux Cluster in Theory and Practice: A Novel Approach in Teaching Cluster Computing Based on the Intel Atom Platform

引用

Procedia computer science 2011年 4卷 1917-1926页

作者： Andy Georgi Stefan Höhlig Robin Geyer Wolfgang E. Nagel Technische Universiẗat Dresden Faculty of Computer Science Chair of Computer Architecture

Current trends and studies on future architectures show, that the complexity of parallel computer systems is increasing steadily. Hence, the industry requires skilled employees, who have in addition to the theoretical fundamentals, practical experiences in the design and administration of such systems. However, investigations have shown, that practical approaches are still missing in current curricula, especially in these areas. For this reason, the chair of computer architecture at the faculty of computer science at the Technische Universiẗat Dresden, developed and introduced the course “Linux Cluster in Theory and Practice” (LCTP). The main objectives of this course are to provide background knowledge about the design and administration of large-scale parallel computer systems and the practical implementation on the available hardware. In addition, students learn how to solve problems in a structured approach and as part of a team. This paper analyzes the current variety of courses in the area of parallel computing systems, describes the structure and implementation of LCTP and provides first conclusions and an outlook on possible further developments.

关键词： Teaching Practical course Systems engineering Systems administration Parallel computer systems

来源：评论

学校读者我要写书评

暂无评论

Information Storage 1

引用

1000年

作者： Cornelia S. Große Rolf Drechsler

来源：评论

学校读者我要写书评

暂无评论

Comparison of common parallel architectures for the execution of the island model and the global parallelization of evolutionary algorithms

Comparison of common parallel architectures for the executio...

引用

作者： Limmer, Steffen Fey, Dietmar Chair of Computer Architecture Friedrich-Alexander University Erlangen-Nürnberg Martensstr. 3 Erlangen91058 Germany

Evolutionary algorithms are one of the most popular forms of optimization algorithms. They are comparatively easy to use and were successfully employed for a wide variety of practical applications. However, frequently, it is necessary to execute them in parallel in order to reduce the runtime. There are a number of different approaches for the parallelization of evolutionary algorithms, and various hardware platforms can be used for the parallel execution. However, not every platform is equally suitable for any kind of parallelization of evolutionary algorithms. In addition, it also depends on properties of the concrete optimization problem to be solved and on the used evolutionary algorithm, which platform is best suited for the execution. The present work observes this in detail for two common forms of parallelization of evolutionary algorithms – the island model and the global parallelization – and for four widely used parallel computing platforms – multi-core CPUs, clusters, graphics cards, and grids. Based on empirical and analytical investigations, it is determined, under which circumstances an architecture is better suited for the execution of a parallel evolutionary algorithm than another (and vice versa). Guidelines are derived that support users of parallel evolutionary algorithms with the choice of an appropriate platform. Copyright © 2016 John Wiley & Sons, Ltd. Copyright © 2016 John Wiley & Sons, Ltd.

关键词： Clustering algorithms

来源：评论

学校读者我要写书评

暂无评论

High Performance Stencil Code Algorithms for GPGPUs

引用

Procedia computer science 2011年 4卷 2027-2036页

作者： Andreas Schäfer Dietmar Fey Chair for Computer Science 3–Computer Architecture Friedrich-Alexander-Universität Erlangen-Nürnberg Erlangen Germany

In this paper we investigate how stencil computations can be implemented on state-of-the-art general purpose graphics processing units (GPGPUs). Stencil codes can be found at the core of many numerical solvers and physical simulation codes and are therefore of particular interest to scientific computing research. GPGPUs have gained a lot of attention recently because of their superior floating point performance and memory bandwidth. Nevertheless, especially memory bound stencil codes have proven to be challenging for GPGPUs, yielding lower than to be expected speedups. We chose the Jacobi method as a standard benchmark to evaluate a set of algorithms on NVIDIA's latest Fermi chipset. One of our fastest algorithms is a parallel wavefront update. It exploits the enlarged on-chip shared memory to perform two time step updates per sweep. To the best of our knowledge, it represents the first successful applicationof temporal blocking for 3D stencils on GPGPUs and thereby exceeds previous results by a considerable margin. It is also the first paper to study stencil codes on Fermi.

关键词： Stencil codes GPU High performance computing Temporal blocking Jacobi solver CUDA

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：