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ARCS 2017;30th International Conference on architecture of Computing Systems

作者： Christian Hartmann Christian Widerspick Dietmar Fey Department of Computer Science Chair of Computer Architecture Friedrich-Alexander-University Erlangen-Nurnberg (FAU)

Recent trends in the automotive sector led to the use of more computing architectures inside the car. The reason for this increase is the usage of new advanced driver assistance systems (ADAS) in order to avoid human made accidents. Headed by Tesla, BMW and Mercedes all vast automobile manufacturer attempt to integrate ADAS systems inside their cars. With increasing system complexity and increasing costs a methodology to determine the functional properties and also to predict the non-functional properties is necessary in the early project stages. In contrast to systems with standard PC solutions, image processing advanced driver assistance systems are part of the embedded field. These systems have strict constraints such as processing time and energy consumption. Nowadays, simulation environments are used to consider the non-functional properties in the early stages of the design phase. These simulators are often inaccurate and have long simulation time for complex systems. In our work we introduce a novel methodology, based on the reuse distance theory to estimate non-functional properties for image processing algorithms in advanced driver assistance systems.

关键词： advanced driver assistance systems (ADAS) image processing algorithm processing time energy consumption Driver Assistance Systems functional characteristics Cars design phases

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Reducing Energy Consumption by Load Aggregation with an Optimized Dynamic Live Migration of Virtual Machines

Reducing Energy Consumption by Load Aggregation with an Opti...

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International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Daniel Versick Djamshid Tavangarian Faculty of Electrical Engineering and Computer Science Chair of Computer Architecture University of Rostock Rostock Germany

Energy consumption of data centers has been in-creasing continuously during the last years due to rising demands of computational power especially in current Grid- and Cloud-Computing systems. One promising approach of reducing this energy consumption is the consolidation of servers by virtualization. Many low loaded computer systems are virtualized and run on few physical servers for reducing the number of energy-consuming computers. At present this consolidation is usually done statically, thus, the administrator of a data center manually migrates many virtual machines with low load onto one physical server which may lead to overloading when the workload is rising unexpectedly. Dynamic server migration that adapts the number of running physical machines to the current workload overcomes these problems. Physical machines can be highly loaded and in case of further rising load virtual machines are migrated to other physical server systems that have been switched on. Such dynamic load aggregation approaches are rarely used and typically only consider few criteria for migration. This paper presents a classification of migration criteria for live migration of virtual machines in load aggregation environments and proposes an algorithm for combining many different kinds of migration criteria to a clustering-based metric. Thus, the novel load aggregation algorithm optimizes energy consumption as well as other migration criteria like runtime performance of applications.

关键词： Virtual machining Servers Software Clustering algorithms Hardware Energy consumption Partitioning algorithms

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Akers's wavefront planner — One of the fastest stencil-based path planners on FPGAs

Akers's wavefront planner — One of the fastest stencil-base...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Michael Schmidt Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universitat Erlangen-Nuremberg Germany

The efficient and fast processing of path planning algorithms based on stencil codes is a great challenge. On the one hand, these iterative approaches are advantageous because of their regular processing pattern and the characteristic to avoid problems of other path planning methods, like local minima in potential field algorithms. On the other hand, they are computational- and data-intensive because of their high number of required iterations. By comparing several algorithms based on stencil codes, we found one of the fastest and most efficient path planners for realization on FPGAs, Akers's wavefront planner. A processing of 33 maps per second with a resolution of 1024×1024 is possible on a midsize Virtex-5 FPGA achieved through a column-based processing scheme combined with an efficient internal data storage.

关键词： computer architecture Microprocessors Field programmable gate arrays Path planning Clocks Registers Robots

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An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels

An Optimized FPGA Implementation for a Parallel Path Plannin...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Michael Schmidt Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universitat Erlangen-Nuremberg Germany

Path Planning is one of the most computationally intensive tasks in robot systems and a challenge in dynamically changing environments. By means of FPGAs it is possible to process time-critical and data-intensive tasks in robot systems efficiently. We have developed a parallel path planning algorithm which is based on Marching Pixels, an organic computing principle. The algorithm is optimized for FPGA-based processing. A parallel implementation approach together with an efficient buffering of the map data allowed us to obtain a processing rate suitable for real time applications, even for higher resolutions. We achieved a processing rate of 80 maps per second for VGA resolution (640 × 480) on a midsize Virtex-5 FPGA.

关键词： Field programmable gate arrays Robots Pixel Path planning Skeleton Collision avoidance Clocks

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Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

arXiv

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arXiv 2016年

作者： Fey, Dietmar Chair Computer Architecture Martensstr. 3 Erlangen91058 Germany

This paper investigates the potentials of using a hybrid memristor CMOS technology, called MeMOS, for the realisation of ternary adders. Ternary adders exploit the qualitative advantage of multi-value storage capability of memristors compared to conventional CMOS flip-flops storing only binary values in one cell. Furthermore they carry out an addition in O(1) and are therefore considered. The MeMOS approach is compared to a CMOS solution for the ternary adders using multi value memristors as registers concerning the achievable latency and the energy consumption. It is shown that using the TEAM, VTEAM model and a model considering commercially available memristors from Known the approach of using CMOS ternary adders using memristors as multi-value register memory is to prefer. MeMOS circuits have advantages for a static operation mode, i.e. if they are operated after a reset. Copyright © 2016, The Authors. All rights reserved.

关键词： Adders

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Embedded Parallel Computing Accelerators for Smart Control Units of Frequency Converters

Embedded Parallel Computing Accelerators for Smart Control U...

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ARCS 2016;29th International Conference on architecture of Computing Systems

作者： Steffen Vaas Marc Reichenbach Johannes Hofmann Thomas Stadelmayer Dietmar Fey Department of Computer Science Chair of Computer Architecture Friedrich-Alexander-University Erlangen-Nurnberg (FAU)

Classical frequency converters are designed as embedded devices optimized for a specific application-field. But in times of Industry 4.0 simple frequency converters change to smart control units and become more intelligent with analysis and reporting functions to build up smart grids in automation systems for reducing maintenance costs and increasing productivity. To realize these new functions, an evaluation is needed, which kind of computer architectures should be used for these new devices. Due to more complex algorithms, classical microcontrollers are not sufficient anymore. Therefore, we show in this paper, if and how microprocessors in smart control units can benefit from highly parallel hardware accelerators. Consequently, we propose to increase the performance of an ARM Cortex-A9 processor by using an Epiphany III E16 many-core processor as hardware accelerator for complex analysis tasks. Our results show, that a speedup of 1.78 can be achieved, while the power consumption is increased by only 9%.

关键词： Smart Sensors Many-Core Processor Heterogeneous Processor architecture Epiphany Parallella Embedded Preprocessing intelligent sensors Frequency converters control unit hardware accelerator Maintenance costs quad-issue processor Multi-core processors computer architecture Embedded device automation system Smart grids Power consumption macroprocessor Accelerators

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A Simulator Concept for Cloud Computing Infrastructure

A Simulator Concept for Cloud Computing Infrastructure

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6th International Image Processing and Communications Conference, IPandC 2014

作者： Hanczewski, Slawomir Kedzierska, Marta Piechowiak, Maciej Chair of Communication and Computer Networks Poznan University of Technology Polanka 3 60-965 Poznan Poland Institute of Mechanics and Applied Computer Science Kazimierz Wielki University Kopernika 1 85-074 Bydgoszcz Poland

ISBN: (纸本)9783319106618

This paper presents a concept for a simulator for cloud computing environment. According to the assumptions, and in intention, the simulator will make studies on cloud efficiency (from the cloud operator's perspective) possible. One of its possible applications will be then the evaluation of cloud effectiveness in a situation where, for example, new services have been introduced or existing service parameters have been changed. Results obtained by this simulator can be also used in validation and verification of analytical models proposed for a cloud environment. © Springer International Publishing Switzerland 2015.

关键词： Simulators

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H2-MARL: Multi-Agent Reinforcement Learning for Pareto Optimality in Hospital Capacity Strain and Human Mobility during Epidemic

arXiv

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arXiv 2025年

作者： Luo, Xueting Deng, Hao Yang, Jihong Shen, Yao Guo, Huanhuan Sun, Zhiyuan Liu, Mingqing Wei, Jiming Zhao, Shengjie School of Computer Science and Technology Tongji University Shanghai201804 China China Land Surveying and Planning Institute Beijing100035 China College of Architecture and Urban Planning Tongji University Shanghai200092 China Chongqing Institute of Planning and Natural Resources Investigation and Monitoring Chongqing401121 China Li-Fi Research and Development Centre University of Cambridge CambridgeCB3 0FA United Kingdom Guangdong Urban-rural Planning and Design Research Institute Technology Group Co. Ltd. Guangzhou510290 China Engineering Research Center of Key Software Technologies for Smart City Perception and Planning Ministry of Education Shanghai201804 China

The necessity of achieving an effective balance between minimizing the losses associated with restricting human mobility and ensuring hospital capacity has gained significant attention in the aftermath of COVID-19. Reinforcement learning (RL)-based strategies for human mobility management have recently advanced in addressing the dynamic evolution of cities and epidemics;however, they still face challenges in achieving coordinated control at the township level and adapting to cities of varying scales. To address the above issues, we propose a multi-agent RL approach that achieves Pareto optimality in managing hospital capacity and human mobility (H2-MARL), applicable across cities of different scales. We first develop a township-level infection model with online-updatable parameters to simulate disease transmission and construct a city-wide dynamic spatiotemporal epidemic simulator. On this basis, H2-MARL is designed to treat each division as an agent, with a trade-off dual-objective reward function formulated and an experience replay buffer enriched with expert knowledge built. To evaluate the effectiveness of the model, we construct a township-level human mobility dataset containing over one billion records from four representative cities of varying scales. Extensive experiments demonstrate that H2-MARL has the optimal dual-objective trade-off capability, which can minimize hospital capacity strain while minimizing human mobility restriction loss. Meanwhile, the applicability of the proposed model to epidemic control in cities of varying scales is verified, which showcases its feasibility and versatility in practical applications. Copyright © 2025, The Authors. All rights reserved.

关键词： Reinforcement learning

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Waking OA's "slumbering giant": The university's mandate to mandate open access

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New Review of Information Networking 2008年第1期14卷 51-68页

作者： Harnad, Stevan Canada Research Chair in Cognitive Sciences School of Electronics and Computer Science Universite du Québec À Montréal Canada Canada Research Chair Institute of Cognitive Sciences Universite du Québec À Montréal CP 8888 Succursale Centre-Ville Montreal QC H3C 3P8 Canada

Universities (the universal research-providers) as well as research funders (public and private) are beginning to make it part of their mandates to ensure not only that researchers conduct and publish peer-reviewed research (publish or perish), but that they also make it available online, free for all. This is called Open Access (OA), and it maximizes the uptake, impact, and progress of research by making it accessible to all potential users worldwide, not just those users whose universities can afford to subscribe to the journal in which it is published. Researchers can provide OA to their published journal articles by self-archiving them in their own university's online repository. Students and junior faculty-the next generation of research providers and consumers-are in a position to help accelerate the adoption of OA self-archiving mandates by their universities, ushering in the era of universal OA. © 2008 Taylor & Francis.

关键词： Publishing

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Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support

Hardware-Oriented Algebraic Fault Attack Framework with Mult...

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Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)

作者： Maël Gay Tobias Paxian Devanshi Upadhyaya Bernd Becker Ilia Polian Chair of Hardware Oriented Computer Science University of Stuttgart Stuttgart Germany Chair of Computer Architecture University of Freiburg Freiburg Germany

The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.

关键词： Circuit faults Integrated circuit modeling Ciphers Mathematical model Hardware Analytical models Tools

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