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DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations

DRVS: Power-efficient reliability management through Dynamic...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Mohammad Salehi Mohammad Khavari Tavana Semeen Rehman Florian Kriebel Muhammad Shafique Alireza Ejlali Jörg Henkel ESRLab Department of Computer Engineering Sharif University of Technology Tehran Iran Chair for Embedded Systems (CES) Karlsruhe Institute of Technology (KIT) Germany Department of Electrical and Computer Engineering. George Mason University Fairfax Virginia USA

Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling (DRVS) considering process variations in hardware, and diversities in software vulnerability and execution time properties. Experiments show that DRVS system provides significant reliability improvements while providing up to 60% reduced power consumption compared to state-of-the-art techniques.

关键词： Redundancy Timing Software reliability Power demand Tunneling magnetoresistance Software

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SuperNet: Multimode interconnect architecture for manycore chips

SuperNet: Multimode interconnect architecture for manycore c...

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Design Automation Conference

作者： Haseeb Bokhari Haris Javaid Muhammad Shafique Jörg Henkel Sri Parameswaran School of Computer Science and Engineering University of New South Wales Sydney Australia Google Inc. USA Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany

Designers of the on-chip interconnect for manycore chips are faced with the dilemma of meeting performance, power and reliability requirements for different operational scenarios. In this paper, we propose a multimode on-chip interconnect called SuperNet. This interconnect can be configured to run in three different modes: energy efficient mode; performance mode; and, reliability mode. Our proposed interconnect is based on two parallel multi-vt optimized packet switched network-on-chip (NoC) meshes. We describe the circuit design techniques and architectural modifications required to realize such a multimode interconnect. Our evaluation with diverse set of applications show that the energy efficient mode can save on average 40% NoC power, whereas the performance mode can improve the core IPC by up to 13% on selected high MPKI applications. The reliability mode provides protection against soft errors in the router's data path through byte oriented SECDED codes that can correct up to 8 bit errors and detect up to 16 bit errors in a 64 bit flit, whereas the router's control path is protected through DMR lock step execution.

关键词： Frequency modulation Reliability computer architecture System-on-chip Switches Microprocessors

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Malleable NoC: Dark silicon inspired adaptable Network-on-Chip 15

Malleable NoC: Dark silicon inspired adaptable Network-on-Ch...

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Design, Automation and Test in Europe Conference and Exhibition

ISBN: (纸本)9783981537048

Network on Chip (NoC) has been envisioned as a scalable fabric for many core chips. However, NoCs can consume a considerable share of chip power. Moreover, diverse applications are executed in these multicore, where each application imposes a unique load on the NoC. To realise a NoC which is Energy and Delay efficient, we propose combining multiple VF optimized routers for each node (in traditional NoCs, we have only a single router per node) for efficient NoC for Dark Silicon chips. We present a generic NoC with routers designed for different VF levels, which are distributed across the chip. At runtime, depending on application profile, we combine these VF optimized routers to form constantly changing energy efficient NoC fabric. We call our architecture Malleable NoC. In this paper, we describe the architectural details of the proposed architecture and the runtime algorithms required to dynamically adapt the NoC resources. We show that for a variety of multi program benchmarks executing on Malleable NoC, Energy Delay product (EDP) can be reduced by up to 46% for widely differing workloads. We further show the effect on EDP savings for differing amounts of dark silicon area budget.

关键词： Switches Silicon Multicore processing System-on-chip Runtime Clocks

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High-speed enoding/decoding technique for reliable data transmission in wireless sensor networks

High-speed enoding/decoding technique for reliable data tran...

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IEEE Communications Society Conference on Sensor and Ad Hoc Communications and Networks (SECON)

作者： M. Sammer Srouji Talal Bonny Jörg Henkel Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany Department of Electrical & Computer Engineering University of Sharjah Sharjah UAE

Reliability has become one of the most vital requirements in wireless sensor networks (WSNs). One efficient way to increase the reliability is by using erasure coding techniques such as Reed-Solomon/Cauchy Reed-Solomon. The problem is the time required for encoding and decoding the data words, especially when large amount of data need to be sent like in complex WSN applications. In this paper, we propose HSC, a high-speed coding technique for reliable data transmission and we show that it reduces the number of XORs required for encoding by more than 94% (and consequently the encoding time) in comparison to the number of XORs required by Cauchy Reed-Solomon encoding. In addition, we present a new transmission scheme that works along with HSC to add redundancy on any size of a data load.

关键词： Encoding Vectors Wireless sensor networks Reed-Solomon codes Decoding Reliability Equations

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Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures

Module diversification: Fault tolerance and aging mitigation...

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IEEE International Test Conference

作者： Hongyan Zhang Lars Bauer Michael A. Kochte Eric Schneider Claus Braun Michael E. Imhof Hans-Joachim Wunderlich Jörg Henkel Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany

ISBN: (纸本)9781479908608

Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.

关键词： Stress Circuit faults Aging Runtime Field programmable gate arrays Containers Reliability

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DHASER: Dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems 13

DHASER: Dynamic heterogeneous adaptation for soft-error resi...

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IEEE International Conference on computer-Aided Design

作者： Tuo Li Muhammad Shafique Semeen Rehman Jude Angelo Ambrose Jörg Henkel Sri Parameswaran School of Computer Science and Engineering University of New South Wales Australia Chair for Embedded Systems Karlsruhe Institute of Technology Germany

ISBN: (纸本)9781479910694

Soft error has become a major adverse effect in CMOS based electronic systems. Mitigating soft error requires enhancing the underlying system with error recovery functionality, which typically leads to considerable design cost overhead, in terms of performance, power and area. For embedded systems, where stringent design constraints apply, such cost must be properly bounded. In this paper, we propose a HW/SW methodology DHASER, which enables efficient error recovery functionality for embedded ASIP-based multi-core systems. DHASER consists of three main parts: task level correctness (TLC) analysis, TLC-based processor/core customization, and runtime reliability-aware task management mechanism. It enables each individual ASIP-based processing core to dynamically adapt its specific error recovery functionality according to the corresponding task's characteristics (i.e., soft error vulnerability and execution time deadline). The goal is to optimize the overall system reliability while considering performance/throughput. The experimental results have shown that DHASER can significantly improve the reliability of the system, with little cost overhead, in comparison to the state-of-art counterparts.

关键词： Runtime Multicore processing Redundancy Adaptation models Optimization

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High-level modeling and synthesis for embedded FPGAs 13

High-level modeling and synthesis for embedded FPGAs

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Design, Automation and Test in Europe Conference and Exhibition

作者： Xiaolin Chen Shuai Li Jochen Schleifer Thomas Coenen Anupam Chattopadhyay Gerd Ascheid Tobias G. Noll Institute for Communication Technologies and Embedded Systems RWTH Aachen University Germany Chair of Electronical Engineering and Computer Systems RWTH Aachen University Germany

ISBN: (纸本)9781450321532

The fast evolving applications in modern digital signal processing have an increasing demand for components which have high computational power and energy efficiency without compromising the flexibility. embedded FPGA, which is the customized FPGA with heterogeneous fine-grained application specific operations and routing resources, has shown significantly improved efficiency in terms of throughput, power dissipation and chip area for the target application domain. On the other hand, the complexity of such architecture makes it difficult to perform an efficient architecture exploration and application synthesis without tool support. In this work, we propose a framework for the design of embedded FPGA (eFPGA) architectures, which is extended from an existing framework for Coarse-Grained Reconfigurable architectures (CGRAs). The framework is composed of a high-level modeling formalism for eFPGAs to explore the mapping space, and a retargetable application synthesis flow. To enable fast design space exploration, a force-directed placement algorithm is proposed. Finally, we demonstrate the efficacy of this framework with demanding application kernels.

关键词： Routing Manuals computer architecture Delays Field programmable gate arrays Solid modeling Kernel

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Formal verification of distributed dynamic thermal management 13

Formal verification of distributed dynamic thermal managemen...

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IEEE International Conference on computer-Aided Design

作者： Muhammad Ismail Osman Hasan Thomas Ebi Muhammad Shafique Jörg Henkel School of Electrical Engineering and Computer Science National University of Sciences and Technology Islamabad Pakistan Chair for Embedded Systems (CES) Karlsruhe Institute of Technology (KIT) Germany

ISBN: (纸本)9781479910694

Simulation is the state-of-the-art analysis technique for distributed thermal management schemes. Due to the numerous parameters involved and the distributed nature of these schemes, such non-exhaustive verification may fail to catch functional bugs in the algorithm or may report misleading performance characteristics. To overcome these limitations, we propose a methodology to perform formal verification of distributed dynamic thermal management for many-core systems. The proposed methodology is based on the SPIN model checker and the Lamport timestamps algorithm. Our methodology allows specification and verification of both functional and timing properties in a distributed many-core system. In order to illustrate the applicability and benefits of our methodology, we perform a case study on a state-of-the-art agent-based distributed thermal management scheme.

关键词： Timing Model checking System recovery Computational modeling Thermal management Analytical models Automata

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Transparent structural online test for reconfigurable systems

Transparent structural online test for reconfigurable system...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Mohamed S. Abdelfattah Lars Bauer Claus Braun Michael E. Imhof Michael A. Kochte Hongyan Zhang Jörg Henkel Hans-Joachim Wunderlich Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany Chair for Embedded Systems Karlsruhe Institute of Technology Germany

FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

关键词： Containers Field programmable gate arrays Testing Table lookup Runtime Random access memory Fabrics

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System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia 11

System-level application-aware dynamic power management in a...

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IEEE International Conference on computer-Aided Design

作者： Haris Javaid Muhammad Shafique Jörg Henkel Sri Parameswaran School of Computer Science and Engineering University of New South Wales Sydney Australia Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9781457713989

System-level dynamic power management (DPM) schemes in Multiprocessor System on Chips (MPSoCs) exploit the idleness of processors to reduce the energy consumption by putting idle processors to low-power states. In the presence of multiple low-power states, the challenge is to predict the duration of the idle period with high accuracy so that the most beneficial power state can be selected for the idle processor. In this work, we propose a novel dynamic power management scheme for adaptive pipelined MPSoCs, suitable for multimedia applications. We leverage application knowledge in the form of future workload prediction to forecast the duration of idle periods. The predicted duration is then used to select an appropriate power state for the idle processor. We proposed five heuristics as part of the DPM and compared their effectiveness using an MPSoC implementation of the H.264 video encoder supporting HD720p at 30 fps. The results show that one of the application prediction based heuristic (MAMAPBH) predicted the most beneficial power states for idle processors with less than 3% error when compared to an optimal solution. In terms of energy savings, MAMAPBH was always within 1% of the energy savings of the optimal solution. When compared with a naive approach (where only one of the possible power states is used for all the idle processors), MAMAPBH achieved up to 40% more energy savings with only 0.5% degradation in throughput. These results signify the importance of leveraging application knowledge at system-level for dynamic power management schemes.

关键词： Multimedia communication History Prediction algorithms Energy consumption Motion estimation Streaming media Clocks

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