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检索条件"机构=Chair of Microelectronic Circuits and Systems National Polytechnic"

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Aging Protected Two Stage CTLE For High Speed Data Recievers

Aging Protected Two Stage CTLE For High Speed Data Recievers

引用

2023 IEEE East-West Design and Test Symposium, EWDTS 2023

作者： Harutyunyan, Sergo S. National Polytechnic University of Armenia Chair of Microelectronic Circuits and Systems Yerevan Armenia

ISBN: (纸本)9798350314847

The proposed architecture protects two stage CTLE from aging phenomena. The solution implements additional devices to set different nodes of the circuit to different intermediate voltage levels and prevent them from high stress operating conditions. The added circuitry is estimated to cost 13% increase of the CTLE layout. Aging simulation results show that after 10-year operation the performance degradation is reduced from 45% to less than 5% due to the added protection system. © 2023 IEEE.

关键词： aging CTLE Neg-C SerDes TDDB

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Foldback Current Limiting in Low-Dropout Voltage Regulators with Aging Analysis Based Operating Envelope

Foldback Current Limiting in Low-Dropout Voltage Regulators ...

引用

2023 IEEE East-West Design and Test Symposium, EWDTS 2023

作者： Sahakyan, Hrayr National Polytechnic University of Armenia Chair of Microelectronic Circuits and Systems Yerevan Armenia

ISBN: (纸本)9798350314847

A design methodology for aging aware foldback current limiting is presented. Traditional constant and foldback limiting techniques are reviewed in the context of hot carrier induced degradation. Aging analysis is performed in 14nm finFET process and the results are used to design an LDO with foldback operating envelope that avoids high stress conditions entirely. Simulation results confirm the functionality and effectiveness of the proposed design. © 2023 IEEE.

关键词： Voltage regulators

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Aging Protected Precision CMOS Current Reference with Process, Supply Voltage and Temperature Compensation

Aging Protected Precision CMOS Current Reference with Proces...

引用

2024 IEEE East-West Design and Test Symposium, EWDTS 2024

作者： Sahakyan, Vahan Soghomonyan, Razmik Harutyunyan, Sergo Sahakyan, Hrayr Galstyan, Arman Katayan, Ashot Institute of Radiophysics and Electronics National Academy of Sciences of Armenia Yerevan Armenia National Polytechnic University of Armenia Microelectronic Circuits and Systems Yerevan Armenia

ISBN: (纸本)9798331515768

A mathematical model has been developed describing the operation of current source achieving current variation that is less than 1-2% from the nominal value. A circuit implementation for the derived equations is presented. Shortcomings of the architecture implemented using lvt only devices are described, and a solution is proposed. The proposed technique demonstrates a substantial reduction in degradation, outperforming previous methods by 36%. This significant improvement is a result of the comprehensive approach to mitigating transistor aging effects, incorporating advanced modeling and simulation techniques, as well as innovative circuit design methodologies. The technique is relevant for modern 5nm and below technology nodes. SPICE analysis performed over the designed circuit shown less than ± 4% variation of the reference current in the-40.1250C temperature range considering the process variations in ±3 sigma range. © 2024 IEEE.

关键词： SPICE

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Reliable All PMOS Voltage Doublers for Low-Voltage Applications

Reliable All PMOS Voltage Doublers for Low-Voltage Applicati...

引用

2024 IEEE East-West Design and Test Symposium, EWDTS 2024

作者： Gomtsyan, Hovhannes Sahakyan, Hrayr Soghomonyan, Razmik Sahakyan, Vahan Voskanyan, Garnik Melikyan, Anush Harutyunyan, Sergo Radio Equipment National Polytechnic University of Armenia European University of Armenia Yerevan Armenia Microelectronic Circuits and Systems National Polytechnic University of Armenia Yerevan Armenia Institute of Radiophysics and Electronics National Academy of Sciences of Armenia Yerevan Armenia Institute of Physics Yerevan State University Yerevan Armenia Microelectronic Circuits and Systems of Communication Means European University of Armenia Yerevan Armenia

ISBN: (纸本)9798331515768

Limitations of traditional charge pump architectures are investigated, particularly in the context of low voltage operation and reliability challenges. To address these challenges, two all PMOS charge pumps are proposed, one with a four-phase clocking scheme and another with a six-phase clocking scheme. The proposed structures offer enhanced protection against voltage overstress and higher efficiency at low supply voltages. Both traditional and proposed pumps are designed in 14nm process using same sized pumping capacitors, equal clock frequency and output loading to fairly evaluate the efficiency and longevity of the different designs. Results demonstrate that the proposed designs can provide high pumping efficiency at low voltage processes without overstress. © 2024 IEEE.

关键词： Charge pump circuits

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Aging Protected Two Stage CTLE For High Speed Data Recievers

Aging Protected Two Stage CTLE For High Speed Data Recievers

引用

East-West Design & Test Symposium (EWDTS)

作者： Sergo S. Harutyunyan Chair of Microelectronic Circuits and Systems National Polytechnic University of Armenia Yerevan Armenia

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Foldback Current Limiting in Low-Dropout Voltage Regulators with Aging Analysis Based Operating Envelope

Foldback Current Limiting in Low-Dropout Voltage Regulators ...

引用

East-West Design & Test Symposium (EWDTS)

作者： Hrayr Sahakyan Chair of Microelectronic Circuits and Systems National Polytechnic University of Armenia Yerevan Armenia

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Aging-Aware Design Method for Reliable Analog Integrated circuits Combining Reliability-Aware Circuit Architectures, Transistor's Threshold Voltage and Operating Point-Dependent Degradation

Aging-Aware Design Method for Reliable Analog Integrated Cir...

引用

2024 IEEE East-West Design and Test Symposium, EWDTS 2024

作者： Melikyan, Vazgen Grigoryan, Gurgen Zheng, Xuefeng Li, Kang Melikyan, Shavarsh Grigoryan, Tigran Microelectronic Circuits and Systems National Polytechnic University of Armenia Yerevan Armenia Yerevan State University Yerevan Armenia Faculty of Integrated Circuit Xidian University Xi'an China University of Bristol Bristol United Kingdom National Polytechnic University of Armenia Yerevan Armenia

ISBN: (纸本)9798331515768

Assessing the reliability of analog and mixedsignal circuits is a crucial component of the integrated circuit (IC) verification process. This evaluation involves not only examining the circuits' current performance but also predicting how their functionality might degrade over time due to aging effects. The process of reliability estimation encompasses a range of tests designed to simulate the long-Term impacts of aging on the circuit's behavior, ensuring that the IC will continue to operate reliably throughout its expected lifecycle. Existing standard analog and mixed-signal blocks were analyzed by considering one or two methods of increasing circuits' reliability. Therefore, analog standard blocks have been examined considering aging effects such as voltage threshold, and operating point-dependent degradation, by using MOSRA models. As operating point-dependent degradation has significant impact on analog block's aging, so it should be taken into account while designing aging-Aware analog ICs. © 2024 IEEE.

关键词： Analog integrated circuits

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Aging Protected Precision CMOS Current Reference with Process, Supply Voltage and Temperature Compensation

Aging Protected Precision CMOS Current Reference with Proces...

引用

East-West Design & Test Symposium (EWDTS)

作者： Vahan Sahakyan Razmik Soghomonyan Sergo Harutyunyan Hrayr Sahakyan Arman Galstyan Ashot Katayan Institute of Radiophysics and Electronics National Academy of Sciences of Armenia Yerevan Armenia Chair of Microelectronic Circuits and Systems National Polytechnic University of Armenia Yerevan Armenia

ISBN: (数字)9798331515768

ISBN: (纸本)9798331515775

A mathematical model has been developed describing the operation of current source achieving current variation that is less than 1-2% from the nominal value. A circuit implementation for the derived equations is presented. Shortcomings of the architecture implemented using lvt only devices are described, and a solution is proposed. The proposed technique demonstrates a substantial reduction in degradation, outperforming previous methods by 36%. This significant improvement is a result of the comprehensive approach to mitigating transistor aging effects, incorporating advanced modeling and simulation techniques, as well as innovative circuit design methodologies. The technique is relevant for modern 5nm and below technology nodes. SPICE analysis performed over the designed circuit shown less than ± 4% variation of the reference current in the -40..1250C temperature range considering the process variations in ±3 sigma range.

关键词： Degradation Temperature distribution Accuracy Simulation Voltage Aging SPICE Mathematical models System-on-chip Transistors

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Reliable All PMOS Voltage Doublers for Low-Voltage Applications

Reliable All PMOS Voltage Doublers for Low-Voltage Applicati...

引用

East-West Design & Test Symposium (EWDTS)

作者： Hovhannes Gomtsyan Hrayr Sahakyan Razmik Soghomonyan Vahan Sahakyan Garnik Voskanyan Anush Melikyan Sergo Harutyunyan Chair of Radio Equipment National Polytechnic University of Armenia European University of Armenia Yerevan Armenia Chair of Microelectronic Circuits and Systems National Polytechnic University of Armenia Yerevan Armenia Institute of Radiophysics and Electronics National Academy of Sciences of Armenia Yerevan Armenia Institute of Physics Yerevan State University Yerevan Armenia Microelectronic Circuits and Systems of Communication Means European University of Armenia Yerevan Armenia

ISBN: (数字)9798331515768

ISBN: (纸本)9798331515775

关键词： Low voltage Charge pumps Memory management Programming Reliability engineering Threshold voltage Reliability Integrated circuit reliability Protection MOS devices

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Aging-Aware Design Method for Reliable Analog Integrated circuits Combining Reliability-Aware Circuit Architectures, Transistor's Threshold Voltage and Operating Point-Dependent Degradation

Aging-Aware Design Method for Reliable Analog Integrated Cir...

引用

East-West Design & Test Symposium (EWDTS)

作者： Vazgen Melikyan Gurgen Grigoryan Xuefeng Zheng Kang Li Shavarsh Melikyan Tigran Grigoryan Chair of Microelectronic Circuits and Systems National Polytechnic University of Armenia Yerevan Armenia Yerevan State University Yerevan Armenia Faculty of Integrated Circuit Xidian University Xi'an China University of Bristol Bristol United Kingdom National Polytechnic University of Armenia Yerevan Armenia

ISBN: (数字)9798331515768

ISBN: (纸本)9798331515775

Assessing the reliability of analog and mixedsignal circuits is a crucial component of the integrated circuit (IC) verification process. This evaluation involves not only examining the circuits’ current performance but also predicting how their functionality might degrade over time due to aging effects. The process of reliability estimation encompasses a range of tests designed to simulate the long-term impacts of aging on the circuit's behavior, ensuring that the IC will continue to operate reliably throughout its expected lifecycle. Existing standard analog and mixed-signal blocks were analyzed by considering one or two methods of increasing circuits’ reliability. Therefore, analog standard blocks have been examined considering aging effects such as voltage threshold, and operating point-dependent degradation, by using MOSRA models. As operating point-dependent degradation has significant impact on analog block's aging, so it should be taken into account while designing aging-aware analog ICs.

关键词： Degradation Analytical models Systematics Design methodology Estimation Aging Reliability engineering Threshold voltage Integrated circuit modeling Standards

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