A novel approach of clock domain crossing solution is presented. For high-frequency conditions traditional approach calls for multiple D-flops for single bit synchronization. The higher the frequency the higher the nu...
详细信息
Over time, the complexity of ICs design increasing which making these designs more error-prone. Verification of Integrated circuits using Verilog lacks the flexibility and reusability of the environment. System Verilo...
详细信息
A solution for fully integrated on-chip resistance calibration method is proposed. The solution uses stable clock frequency as a reference instead of an on-board high precision resistor. This stable clock frequency is...
详细信息
ISBN:
(数字)9798331515768
ISBN:
(纸本)9798331515775
A solution for fully integrated on-chip resistance calibration method is proposed. The solution uses stable clock frequency as a reference instead of an on-board high precision resistor. This stable clock frequency is widely available in communication interfaces where impedance matching is crucial. The accuracy of the calibration is limited by the process variance of the integrated MOSFET capacitor which is much tighter than the variance of on-chip poly, metal, or transistor-based resistances. The capacitor is charged to VDD during the clock pulse via a switch and discharged through the digitally controlled resistance during the passive half-period of the clock. The voltage on the capacitor is monitored via a low offset comparator and when it reaches down to the reference level for the first time the digital controller stops the calibration process and stores the code. The proposed solution achieves ±5 accuracy after parasitic extraction and is well within the ±10% specification of high-speed communication interfaces.
In this paper one of the ways of reducing glitches that are present in the output of a simple CMOS inverter is described. This is done via RC filter. In this filter instead of resistor and capacitor MOS transistors ar...
详细信息
ISBN:
(数字)9781728197135
ISBN:
(纸本)9781728197142
In this paper one of the ways of reducing glitches that are present in the output of a simple CMOS inverter is described. This is done via RC filter. In this filter instead of resistor and capacitor MOS transistors are used, which will reduce the area of the circuit with cost of increased delay. Simulations are done under 1 GHz frequency. Under this condition the glitches were reduced by 76%, going down from 250 mV to 60 mV. All researches and simulations are done using Synopsys Armenia Educational Department's SAED 32/28 nm CMOS technology and HSPICE simulator.
Verification of Integrated circuits using Verilog lacks the flexibility and reusability of the environment. System Verilog provides building blocks and OOP concepts to work with. That allows to create much more flexib...
ISBN:
(数字)9781728197135
ISBN:
(纸本)9781728197142
Verification of Integrated circuits using Verilog lacks the flexibility and reusability of the environment. System Verilog provides building blocks and OOP concepts to work with. That allows to create much more flexible test environment with reusable components. This paper presents a verification architecture of configurable Verification IP for UART interface. The Verification IP presented in this paper provides complete functionality of an operating UART interface and can be used to test any UART device. A functional coverage model has been developed to determine if the verification process covers all possible scenarios or not. Each testcase reports coverage which is later used to analyze the effectiveness of the testcase. Full coverage has been achieved using both random and directed test cases. The coding is done using System Verilog and the simulation is done using VCS.
UART is one of the most widely used interfaces. It is as single bit TX and RX interface which supports multiple configurations. It supports data length of 5-8 bits, even, odd or missing parity bit and 3 more stop bit ...
详细信息
ISBN:
(数字)9781728197135
ISBN:
(纸本)9781728197142
UART is one of the most widely used interfaces. It is as single bit TX and RX interface which supports multiple configurations. It supports data length of 5-8 bits, even, odd or missing parity bit and 3 more stop bit counts. As most UART devices have fixed configuration it usually requires manual configuration of both sides to support proper data transfers. This paper presents a novel design of UART interface that will remove that limitation. Proposed UART controller can detect baud rate automatically and adjust to it. Additionally, there is a new command interface which is used to understand remaining config of the device to fully adapt to the connected device. That will allow any device to connect to proposed UART controller and work without any manual configuration. The UART controller RTL has been developed using Verilog and the test environment was developed using SystemVerilog. Simulations have been done using VCS.
On-chip decoupling capacitors used for reducing power supply noise. In this paper, a design technique for sizing and placing on-chip decoupling cells based on circuits switching activity is proposed. Evaluation of thi...
详细信息
暂无评论