High-probability analysis of stochastic first-order optimization methods under mild assumptions on the noise has been gaining a lot of attention in recent years. Typically, gradient clipping is one of the key algorith...
High-probability analysis of stochastic first-order optimization methods under mild assumptions on the noise has been gaining a lot of attention in recent years. Typically, gradient clipping is one of the key algorithmic ingredients to derive good high-probability guarantees when the noise is heavy-tailed. However, if implemented naïvely, clipping can spoil the convergence of the popular methods for composite and distributed optimization (Prox-SGD/Parallel SGD) even in the absence of any noise. Due to this reason, many works on high-probability analysis consider only unconstrained non-distributed problems, and the existing results for composite/distributed problems do not include some important special cases (like strongly convex problems) and are not optimal. To address this issue, we propose new stochastic methods for composite and distributed optimization based on the clipping of stochastic gradient differences and prove tight high-probability convergence results (including nearly optimal ones) for the new methods. In addition, we also develop new methods for composite and distributed variational inequalities and analyze the high-probability convergence of these methods.
To ensure the reliability and safety in applications such as aeronautics, automotive, industrial automation, railway and space, several redundancy-based embedded architectures are used. In this work, the design of a 1...
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To ensure the reliability and safety in applications such as aeronautics, automotive, industrial automation, railway and space, several redundancy-based embedded architectures are used. In this work, the design of a 1oo4 safety system-on-Chip based on LEON3 processor with two different design approaches is presented. In both of the approaches, four LEON3 processors with a shared debug support unit, debug link and system peripherals are designed. However, one memory controller is interfaced with the system in the first approach while in the second approach four memory controllers are interfaced. Both the designs are implemented using the XUPV5-XC5VLX110T Xilinx development board (ML509). The performance of the system is verified in this work using the Xilinx ChipScope tool.
Autonomous guided vehicles have major benefits in terms of a rail bound conveyor technology because they are able to respond flexibly to changes in the application area. In many areas, safety-related position detectio...
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Autonomous guided vehicles have major benefits in terms of a rail bound conveyor technology because they are able to respond flexibly to changes in the application area. In many areas, safety-related position detection is necessary to avoid accidents. Derived from this position the driving speed in the work areas can be reduced in a safe way and minimum distances can also be observed in a safe manner. For this purpose, it is necessary to permanently control the measured position with regard to the disturbance variables and precision of measurements and in case of a deviation they have to be corrected in a highly reliable way. The solutions that are known so far do all imply two sensors that monitor each other. In the approach shown here, the required diagnostic coverage for a safety-related position determination is achieved through the use of only one laser scanner as well as through the help of algorithms that are implemented in a safety-related evaluation control. The focus of this paper is set on the position and orientation errors that are caused by measurement deviations.
Application specific integrated circuits (ASICs), which represent a target platform for safety-related applications, were already covered in the first edition of the standard IEC 61508 in terms of functional safety. C...
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Application specific integrated circuits (ASICs), which represent a target platform for safety-related applications, were already covered in the first edition of the standard IEC 61508 in terms of functional safety. Corresponding requirements are introduced in part 2 of the standard. However, using ASICs with on-chip redundancy for safety applications has been introduced only in subsequent drafts of the standard. Corresponding core requirements for on-chip redundancy for ASICs are explained in the second edition of the standard. The theoretical conclusions and analyses have been implemented in several research projects based on a redundant system architecture consisting of two RISC cores with a hardware comparator as a diagnosis unit. In this paper, the implementation of safety-related on-chip systems will be discussed on the basis of the theoretical requirements of the standard as well as on the basis of practice-related experiences.
In this paper a complete safety controller on a single chip is introduced. The presented chip is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applicati...
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In this paper a complete safety controller on a single chip is introduced. The presented chip is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applications according to the safety standard IEC 61508, meeting the safety integrity level SIL3. Furthermore, a SIL3 operating system and a SIL3 middleware are also briefly presented in this paper. Based on the presented solution, the smallest certified safety controller represents an innovative product and allows system manufacturers to create safe solutions that are ready for certification.
This paper describes the implementation and integration process of a complete communication computer system on the field programmable gate array (FPGA). After such a design is reached, safety measures are integrated t...
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This paper describes the implementation and integration process of a complete communication computer system on the field programmable gate array (FPGA). After such a design is reached, safety measures are integrated to achieve a safety-related architecture. For this purpose a diagnostic unit will be implemented, consisting of hardware and software tests. Hardware tests are related to the control of the FPGA functionality. They are based on the integration of two existing methods to reach complete hardware test coverage. The software tests are used for a continuous testing of the whole system (this means testing the central processing unit, bus systems, peripherals and memory). Furthermore, a safety multiplexer is integrated with the task to turn off the current operating system (main system) and to turn on a redundant system when a failure is introduced via the diagnostic unit. The safety multiplexer has to give the permission to the redundant system to receive the outputs from the main system in a way that is free from faults. The microcontroller ColdFire is used as a basis, which provides numerous features for the control of various peripherals as well as the connection of various types of memory.
In this paper nl approach of an on-chip safety system architecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnost...
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In this paper nl approach of an on-chip safety system architecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnostic units and is designed to meet the highest possible safety integrity level for on-chip systems. The presented on-chip safety system consists of two redundant processor channels, each of which has a processor unit, data memory, program memory, communication interfaces, inputs and outputs. Furthermore, on-chip diagnosis- and monitoring units and a communication core are integrated. The safety-related implementation of the proposed architecture is introduced in this paper. This includes hardware and software implementation methodologies. Finally, a brief evaluation of the presented architecture is presented.
In this paper a complete safety controller on a single chip is presented. HICore 1 is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applications accordi...
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In this paper a complete safety controller on a single chip is presented. HICore 1 is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applications according to the safety standard IEC 61508, meeting the safety integrity level SIL3. It also meets the requirements of the standard EN 13849 Performance Level e. A SIL3 operating system and a SIL3 middleware complement the presented safety chip solution. Based on the presented solution, the smallest certified safety controller represents an innovative product and allows system manufacturers to create safe solutions ready for certification.
FPGAs introduce a very attractive platform for the designing process of complex embedded systems. The complexity of these systems should be controlled to fulfill high demands and requirements, especially in safety-rel...
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FPGAs introduce a very attractive platform for the designing process of complex embedded systems. The complexity of these systems should be controlled to fulfill high demands and requirements, especially in safety-related applications, where aspects like reliability, availability and safety are of the utmost significance. In this context, the present paper intends the design and implementation of a novel on-chip quadruple redundant safety-related system architecture (1oo4-architecture - one out of four) as a fault tolerant technique to increase the level of safety integrity, reliability and availability of electronic embedded systems. For this aim the 1oo4-architecture and their related safety characteristics are briefly demonstrated. The FPGA-based embedded system model of this novel architecture is developed and explained. The main part of this paper focuses on the safety-related implementation on FPGA. Finally, an evaluation of the implemented architecture concludes this paper.
Wireless sensor networks for monitoring and steering industrial systems have emerged as an important new application area for wireless embedded technology in safety-related systems. Therefore several hardware platform...
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Wireless sensor networks for monitoring and steering industrial systems have emerged as an important new application area for wireless embedded technology in safety-related systems. Therefore several hardware platforms can be targeted. Due to their flexibility and reconfigurability along with high performance and power efficiency, modern Field Programmable Gate Arrays (FPGAs) are an excellent platform to realize such intelligent sensor networks. On one hand, FPGAs can integrate embedded processors and on-chip memory into a single die and can be easily configured to interface with a wide variety of popular communications protocols like SPI, UART and I2C, which are used for sensor communication. On the other hand, the reconfigurability of FPGAs supports the design of self-organizing computing systems, which are increasingly used in sensor applications. In this paper an FPGA-based wireless smart sensor network that integrates acceleration sensors for increasing safety aspects in cognitive systems used for industrial communication is presented.
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