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Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with 4.6μV Precision and 4.1nV/Hz0.5Noise Co-Integrated with the Single Electron Transistor at 60mK 72

Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with 4.6μV Pr...

引用

72nd IEEE International Solid-State Circuits Conference, ISSCC 2025

作者： Li, Yingjie Zhang, Yifei Lin, Haichuan Wang, Cheng University of Electronic Science and Technology of China Chengdu China Southern University of Science and Technology Shenzhen China Chengdu Data Automation System Technologies Chengdu China

ISBN: (纸本)9798331541019

Millions of physical quantum-bits (Qubits) are envisioned for a fault-tolerant quantum computer [1]. Compared with the superconducting Qubit or trapped-ions, the silicon spin Qubits are scaling friendly due to the compatibility with the advanced silicon process. Intel recently reveals the fabrication and 1.6K verification of hundreds of Si/SiGe quantum dots on a 300mm Si wafer [2]. In addition, through the Coulomb blockade, the single electron transistor (SET) controls the flow of the electron between the source and drain to a quantum dot built either by a single phosphorus atom on Silicon [3] or a Si/SiGe heterostructure [4] (Fig. 13.4.1). It plays an important role in the Elzerman readout of Si Qubit states [5]. In both of the Si Qubit and SET, the gate voltage sets the energy barrier for the manipulation of the electron spin. For the single electron device with multiple gates, a high precision voltage bias at the source and drain is required to counteract the undesired source-drain offset, which is around 10μV. Therefore, high precision and low noise gate control is crucial for the high-fidelity quantum logic gate. Furthermore, since the Qubits are hosted on the sub-100mK stage of dilution refrigerator, the cabling from room-temp. (300K) control electronics to Qubits is a significant challenge. To this end, the ultra-low power Cryo-CMOS circuitry emerges as a promising solution [6]. © 2025 IEEE.

关键词： Silicon wafers

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13.4: Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with $4.6\mu\mathrm{V}$ Precision and $4.1 \text{nV}/\text{Hz}^{0.5}$ Noise Co-Integrated with the Single Electron Transistor at 60mK

13.4: Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with $4....

引用

IEEE International Conference on Solid-State Circuits (ISSCC)

作者： Yingjie Li Yifei Zhang Haichuan Lin Cheng Wang University of Electronic Science and Technology of China Chengdu China Southern University of Science and Technology Shenzhen China Chengdu Data Automation System Technologies Chengdu China

ISBN: (数字)9798331541019

ISBN: (纸本)9798331541026

Millions of physical quantum-bits (Qubits) are envisioned for a fault-tolerant quantum computer [1]. Compared with the superconducting Qubit or trapped-ions, the silicon spin Qubits are scaling friendly due to the compatibility with the advanced silicon process. Intel recently reveals the fabrication and 1.6K verification of hundreds of Si/SiGe quantum dots on a 300mm Si wafer [2]. In addition, through the Coulomb blockade, the single electron transistor (SET) controls the flow of the electron between the source and drain to a quantum dot built either by a single phosphorus atom on Silicon [3] or a Si/SiGe heterostructure [4] (Fig. 13.4.1). It plays an important role in the Elzerman readout of Si Qubit states [5]. In both of the Si Qubit and SET, the gate voltage sets the energy barrier for the manipulation of the electron spin. For the single electron device with multiple gates, a high precision voltage bias at the source and drain is required to counteract the undesired source-drain offset, which is around $10\mu \mathrm{V}$ . Therefore, high precision and low noise gate control is crucial for the high-fidelity quantum logic gate. Furthermore, since the Qubits are hosted on the sub-100mK stage of dilution refrigerator, the cabling from room-temp. (300K) control electronics to Qubits is a significant challenge. To this end, the ultra-low power Cryo-CMOS circuitry emerges as a promising solution [6].

关键词： Qubit Quantum dots Noise Logic gates Phosphorus Silicon Solid state circuits Spin qubits Single electron transistors Electrons

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34.5 A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with 202dBc/Hz FoM for Classic-Quantum Interface

34.5 A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with...

引用

2023 IEEE International Solid-State Circuits Conference, ISSCC 2023

作者： Zhang, Gengnanyang Lin, Haichuan Wang, Cheng University of Electronic Science and Technology of China Chengdu China Chengdu Data Automation System Technologies Chengdu China

ISBN: (纸本)9781665428002

Recently, physical quantum-bits (Qubits) have achieved a remarkable operational fidelity >99.9% and a coherence time ranging from milliseconds to seconds with classic quantum controller (300K). Quantum error correction has also been successfully demonstrated. This paves the way towards a scalable, error-corrected quantum computer. However, the manipulation and sensing of large-scale Qubit array with high fidelity are still facing many challenges of error management. One error mechanism is the dephasing of the coherent superposition states of Qubits, induced by the phase noise (PN) of microwave driving pulses [1]. For the X/Y axis rotation in the Bloch sphere, a phase error of 0.57° corresponds to a Qubit fidelity of 99.99% (Fig. 34.5.1) [2]. The cryogenic CMOS phase-locked loops (PLLs) in the pulse generator and reflectometry enjoy a 10sim 100times lower thermal noise, which mitigates the frequency/phase error. However, the cryogenic CMOS voltage-controlled oscillators (VCOs) inside the PLLs suffer from a surprisingly high flicker noise. This is due to the generation-recombination noise with varying relaxation time constant and the shifting trap density with energy. This work presents a calibration-free 12.8-to-16.5GHz cryogenic VCO on 65nm bulk CMOS process. Using an eight-shape head resonator, this VCO achieves 2nd and 3rd harmonic-resonance alignment for flicker noise suppression. Under 4.2K, a highest VCO figure-of-merit (FoM) of 202.3dBc/Hz, a temperature-invariant flicker noise corner frequency of 450sim 950textkHz and a relative bandwidth of 25.1% have been measured. © 2023 IEEE.

关键词： Cryogenics

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A Cryo-CMOS 4.57GHz Dual-Qubit Homodyne Reflectometer Array with High Q Degenerate Parametric Amplifier Through Dynamic Mode Coupling 19

A Cryo-CMOS 4.57GHz Dual-Qubit Homodyne Reflectometer Array ...

引用

19th IEEE Asian Solid-State Circuits Conference, A-SSCC 2023

作者： Geng, Yujie Lin, Haichuan Wang, Bo Wang, Cheng Chengdu China Chengdu Data Automation System Technologies Chengdu China Hamad Bin Khalifa University Doha Qatar

ISBN: (纸本)9798350330038

Error-corrected quantum computing does not only require large-scale (106-109) physical Qubit arrays but also relies on high-fidelity, scalable quantum-to-classic interface electronics. Quantum control and readout systems based on cryogenic CMOS integrated circuits mitigate the error of Qubit manipulation, reduce the cabling complexity, and facilitate the quantum feedback, which pave the way towards practical quantum error correction (QEC) and logic quantum gates. RF reflectometry is widely adopted for qubit states readout. Reflectometry conducts Qubit states discrimination (collapsed to '0' or '1') by detecting the resonant frequency through RF reflection of a high-Q LC tank associated with the sensor Qubit (Fig. 1). The quantum states are encoded in either the amplitude or the phase of the reflected RF signal. Compared with its DC counterpart, the reflectometry achieves unprecedented charge sensitivity, reduces the integration time, and avoids long-term drifting. However, conventional heterodyne reflectometer schemes [1][4][5] adopt sophisticated up/down mixers, ADC, DAC, and PLL for the Qubit excitation and down-mixing, respectively. They suffer from poor TX-RX isolation, inter-modulation, and high DC power, which deteriorate the scalability and readout fidelity. To address these challenges, a highly scalable dual-Qubit homodyne reflectometer array is proposed in this paper. It drives the LC tank by a single PLL and detects the reflection by a high-gain degenerate parametric amplifier (DPA). Along with fast modulation and lock-in detection, it mitigates the interference, complex cabling, and high DC power of conventional heterodyne reflectometers. © 2023 IEEE.

关键词： Reflection

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34.5 A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with 202dBc/Hz FoM for Classic-Quantum Interface

34.5 A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with...

引用

IEEE International Conference on Solid-State Circuits (ISSCC)

作者： Gengnanyang Zhang Haichuan Lin Cheng Wang University of Electronic Science and Technology of China Chengdu China Chengdu Data Automation System Technologies Chengdu China

Recently, physical quantum-bits (Qubits) have achieved a remarkable operational fidelity >99.9% and a coherence time ranging from milliseconds to seconds with classic quantum controller (300K). Quantum error correction has also been successfully demonstrated. This paves the way towards a scalable, error-corrected quantum computer. However, the manipulation and sensing of large-scale Qubit array with high fidelity are still facing many challenges of error management. One error mechanism is the dephasing of the coherent superposition states of Qubits, induced by the phase noise (PN) of microwave driving pulses [1]. For the X/Y axis rotation in the Bloch sphere, a phase error of 0.57° corresponds to a Qubit fidelity of 99.99% (Fig. 34.5.1) [2]. The cryogenic CMOS phase-locked loops (PLLs) in the pulse generator and reflectometry enjoy a $10\sim 100\times$ lower thermal noise, which mitigates the frequency/phase error. However, the cryogenic CMOS voltage-controlled oscillators (VCOs) inside the PLLs suffer from a surprisingly high flicker noise. This is due to the generation-recombination noise with varying relaxation time constant and the shifting trap density with energy. This work presents a calibration-free 12.8-to-16.5GHz cryogenic VCO on 65nm bulk CMOS process. Using an eight-shape head resonator, this VCO achieves 2 nd and 3 rd harmonic-resonance alignment for flicker noise suppression. Under 4.2K, a highest VCO figure-of-merit (FoM) of 202.3dBc/Hz, a temperature-invariant flicker noise corner frequency of $450\sim 950\text{kHz}$ and a relative bandwidth of 25.1% have been measured.

关键词： Voltage-controlled oscillators Qubit Resonant frequency Cryogenics Reflectometry Thermal noise Frequency measurement

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A Cryo-CMOS 4.5~7GHz Dual-Qubit Homodyne Reflectometer Array with High Q Degenerate Parametric Amplifier Through Dynamic Mode Coupling

A Cryo-CMOS 4.5~7GHz Dual-Qubit Homodyne Reflectometer Array...

引用

IEEE Asian Conference on Solid-State Circuits (ASSCC)

作者： Yujie Geng Haichuan Lin Bo Wang Cheng Wang University of Electronic Science and Technology of China (UESTC) Chengdu China Chengdu Data Automation System Technologies Chengdu China Hamad Bin Khalifa University Doha Qatar

Error-corrected quantum computing does not only require large-scale (10 6 –10 9 ) physical Qubit arrays but also relies on high-fidelity, scalable quantum-to-classic interface electronics. Quantum control and readout systems based on cryogenic CMOS integrated circuits mitigate the error of Qubit manipulation, reduce the cabling complexity, and facilitate the quantum feedback, which pave the way towards practical quantum error correction (QEC) and logic quantum gates. RF reflectometry is widely adopted for qubit states readout. Reflectometry conducts Qubit states discrimination (collapsed to “0” or “1”) by detecting the resonant frequency through RF reflection of a high-Q LC tank associated with the sensor Qubit (Fig. 1). The quantum states are encoded in either the amplitude or the phase of the reflected RF signal. Compared with its DC counterpart, the reflectometry achieves unprecedented charge sensitivity, reduces the integration time, and avoids long-term drifting. However, conventional heterodyne reflectometer schemes [1][4][5] adopt sophisticated up/down mixers, ADC, DAC, and PLL for the Qubit excitation and down-mixing, respectively. They suffer from poor TX-RX isolation, inter-modulation, and high DC power, which deteriorate the scalability and readout fidelity. To address these challenges, a highly scalable dual-Qubit homodyne reflectometer array is proposed in this paper. It drives the LC tank by a single PLL and detects the reflection by a high-gain degenerate parametric amplifier (DPA). Along with fast modulation and lock-in detection, it mitigates the interference, complex cabling, and high DC power of conventional heterodyne reflectometers.

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