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International Conference on Computer and Information technology (CIT)

作者： Xiaofei Liao Fan Zhang Hai Jin Linchen Yu Cluster and Grid Computing Laboratory Services Computing Technology and System Laboratory School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China China University of Geoscience Wuhan China

Peer-to-peer (P2P) on-demand streaming systems inevitably suffer from peers churn that is the inherent dynamic characteristic of overlay network. With frequent peer departure, a large amount of media data cached on peer disk turns offline and unavailable, which becomes the major reason of heavy server load. To address the above issue, a new proactive data replication mechanism is proposed and implemented in existing P2P on-demand system GirdCast. Based on the new mechanism, peer can proactively replicate data chunks to stable cache servers for future sharing, when it has high possibility to leave the overlay. Two key heuristic algorithms are designed for departure prediction and replicated chunks selection. system trace driven simulation shows that the mechanism greatly decreases bandwidth load of media source server and improves the availability of chunks highly demanded but poorly provisioned by overlay peers.

关键词： Servers Peer to peer computing Media Availability Streaming media Bandwidth Distributed databases

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Research on Architecture of grid-Based Simulation Platform

Research on Architecture of Grid-Based Simulation Platform

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Japan-china Joint Workshop on Frontier of Computer Science and technology (FCST)

作者： Song Wu Li Qi Hai Jin Heng He Key Lab of Cluster and Grid Computing Key Lab of Service Computing Technology and System Ministry of Education Huazhong University of Science and Technology Wuhan Hubei China

This paper proposes a grid-based Distributed Simulation Platform (GDSP). It is designed to break the limitation of legacy simulation supporting platform and to meet new requirements from large-scale, distributed, and complicated systems. Simulation services are encapsulated by using web services technology, and they are basic elements of GDSP. With grid technology, GDSP enables users to share, access, and operate remote resource transparently. It is also easier to organize and manage simulation resources. GDSP improves the capability of fault tolerance and provides mechanism of using simulation resources securely. The research result shows that through this management mechanism, multiple users can share and monitor RTI resources, and manage the simulation collaboratively and effectively. At the same time, the impact on real time of RTI caused by the system is minimum.

关键词： Computational modeling Resource management Web services Computer architecture Application software Large-scale systems Fault tolerance Distributed computing Context modeling Runtime

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A General Offloading Approach for Near-DRAM Processing-In-Memory Architectures

A General Offloading Approach for Near-DRAM Processing-In-Me...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Dan Chen Hai Jin Long Zheng Yu Huang Pengcheng Yao Chuangyi Gui Qinggang Wang Haifeng Liu Haiheng He Xiaofei Liao Ran Zheng National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Clusters and Grid Computing Lab Huazhong University of Science and Technology China

Processing-in-memory (PIM) is promising to solve the well-known data movement challenge by performing in-situ computations near the data. Leveraging PIM features is pretty profitable to boost the energy efficiency of applications. Early studies mainly focus on improving the programmability for computation offloading on PIM architectures. They lack a comprehensive analysis of computation locality and hence fail to accelerate a wide variety of applications. In this paper, we present a general-purpose instruction-level offloading technique for near-DRAM PIM architectures, namely IOTPIM, to exploit PIM features comprehensively. IOTPIM is novel with two technical advances: 1) a new instruction offloading policy that fully considers the locality of the whole on-chip cache hierarchy, and 2) an offloading performance benefit prediction model that directly predicts offloading performance benefits of an instruction based on the input dataset characterizes, preserving low analysis overheads. The evaluation demonstrates that IOTPIM can be applied to accelerate a wide variety of applications, including graph processing, machine learning, and image processing. IOT-PIM outperforms the state-of-the-art PIM offloading techniques by 1.28×-1.51× while ensuring offloading accuracy as high as 91.89% on average.

关键词： Analytical models Technological innovation Distributed processing systematics Image processing Computer architecture Machine learning

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An Efficient Block Validation Mechanism for UTXO-based Blockchains

An Efficient Block Validation Mechanism for UTXO-based Block...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Xiaohai Dai Bin Xiao Jiang Xiao Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Department of Computing The Hong Kong Polytechnic University Hong Kong

It has been recognized that one of the bottlenecks in the UTXO-based blockchain systems is the slow block validation - the process of validating a newly-received block by a node before locally storing it and further broadcasting it. As a block contains multiple inputs, the block validation mainly involves checking the inputs against the status data, which is also known as the Unspent Transaction Outputs (UTXO) set. As time goes by, the UTXO set becomes more and more expansive, most of which can only be stored on disks. This considerably slows down the input checking and thus block validation, which can potentially compromise system security. To deal with the above problem, we disassemble the function of input checking into three parts: existence validation (EV), unspent validation (UV), and script validation (SV). Based on the disassembly, we propose EBV, an efficient block validation mechanism to speed up EV, UV, and SV individually. First, EBV changes the representation of status data, from UTXO set to a bit-vector set, which drastically reduces its size. The smaller status data can be entirely maintained in memory, thereby accelerating UV and also block validation. Second, EBV requires each transaction to carry the proof data, which enables EV and SV without accessing the disks. Furthermore, we also cope with two challenges in the design of EBV, namely transaction inflation and fake positions. To evaluate the EBV mechanism, we implement a prototype on top of Bitcoin, the most widely known UTXO-based blockchain, and conduct extensive experiments to compare EBV and Bitcoin. The experimental results demonstrate that EBV successfully reduces the memory requirement by 93.1 % and the block validation time by up to 93.5%.

关键词： Distributed processing Memory management Prototypes Bitcoin Broadcasting Blockchains Delays

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Near-duplicate detection using GPU-based simhash scheme

Near-duplicate detection using GPU-based simhash scheme

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International Conference on Smart computing (SMARTCOMP)

作者： Xiaowen Feng Hai Jin Ran Zheng Lei Zhu Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Information & Communication Company of Hunan Electric Power Corporation Changsha Hunan China

ISBN: (纸本)9781479957125

With the rapid growth of data, near-duplicate documents bearing high similarity are abundant. Elimination of near-duplicates can reduce storage cost and improve the quality of search indexes in data mining. A challenging problem is to find near-duplicate records in large-scale collections efficiently. There have already been several efforts on implementing near-duplicate detection on different architectures. In this paper, a new implementation, using a special hash function namely simhash, is proposed to identify near-duplicate documents on CUDA enabled devices. Two mechanisms are designed to achieve higher performance, including swapping and dynamic allocating. Experimental results show that our parallel implementation outperforms the serial CPU version, achieving up to 18 times.

关键词： Graphics processing units Fingerprint recognition Instruction sets Hamming distance Dynamic scheduling Kernel Computer architecture

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Layered Structure Aware Dependent Microservice Placement Toward Cost Efficient Edge Clouds

Layered Structure Aware Dependent Microservice Placement Tow...

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IEEE Annual Joint Conference: INFOCOM, IEEE Computer and Communications Societies

作者： Deze Zeng Hongmin Geng Lin Gu Zhexiong Li School of Computer Science China University of Geosciences Wuhan China National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Although the containers are featured by light-weightness, it is still resource-consuming to pull and startup a large container image, especially in relatively resource-constrained edge cloud. Fortunately, Docker, as the most widely used container, provides a unique layered architecture that allows the same layer to be shared between microservices so as to lower the deployment cost. Meanwhile, it is highly desirable to deploy dependent microservices of an application together to lower the operation cost. Therefore, the balancing of microservice deployment cost and the operation cost should be considered comprehensively to achieve minimal overall cost of an on-demand application. In this paper, we first formulate this problem into a Quadratic Integer Programming form (QIP) and prove it as a NP-hard problem. We further propose a Randomized Rounding-based Microservice Deployment and Layer Pulling (RR-MDLP) algorithm with low computation complexity and guaranteed approximation ratio. Through extensive experiments, we verify the high efficiency of our algorithm by the fact that it significantly outperforms existing state-of-the-art microservice deployment strategies.

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Significant Engagement Community Search on Temporal Networks: Concepts and Algorithms

arXiv

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arXiv 2022年

作者： Zhang, Yifei Lin, Longlong Yuan, Pingpeng Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science & Technology HuaZhong University of Science and Technology Luoyu Road 1037 Hubei Wuhan430074 China

Community search, retrieving the cohesive subgraph which contains the query vertex, has been widely touched over the past decades. The existing studies on community search mainly focus on static networks. However, real-world networks usually are temporal networks where each edge is associated with timestamps. The previous methods do not work when handling temporal networks. We study the problem of identifying the significant engagement community to which the user-specified query belongs. Specifically, given an integer k and a query vertex u, then we search for the subgraph H which satisfies (i) u ∈ H;(ii) the de-temporal graph of H is a connected k-core;(iii) In H that u has the maximum engagement level. To address our problem, we first develop a top-down greedy peeling algorithm named TDGP, which iteratively removes the vertices with the maximum temporal degree. To boost the efficiency, we then design a bottom-up local search algorithm named BULS and its enhanced versions BULS+ and BULS*. Lastly, we empirically show the superiority of our proposed solutions on six real-world temporal graphs. Copyright © 2022, The Authors. All rights reserved.

关键词： Iterative methods

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Design Automation Conference

作者： Jin Zhao Yu Zhang Jian Cheng Yiyang Wu Chuyue Ye Hui Yu Zhiying Huang Hai Jin Xiaofei Liao Lin Gu Haikun Liu National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Zhejiang-HUST Joint Research Center for Graph Processing Zhejiang Lab Hangzhou China

Temporal graph processing is used to handle the snapshots of the temporal graph, which concerns changes in graph over time. Although several software/hardware solutions have been designed for efficient temporal graph processing, they still suffer from serious irregular data access due to the uncoordinated graph traversal. To overcome these limitations, this paper proposes SaGraph, a domain-specific hardware accelerator to support the efficient processing of temporal graph. Specifically, temporal graph processing shows strong data access similarity, i.e., most graph accesses of the processing of different snapshots are the same and usually refer to a small fraction of vertices. SaGraph can dynamically coordinate the graph traversals and adaptively cache the vertex states to fully exploit the data access similarity for smaller data access overhead. We implemented and evaluated SaGraph on a Xilinx Alveo U280 FPGA card. Compared with the cutting-edge software and hardware solutions, SaGraph achieves 8.5×-157.3×, 4.2×-16.1× speedups and 34.7×-423.6×, 5.3×-14.7× energy savings, respectively.

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Spara: An Energy-Efficient ReRAM-Based Accelerator for Sparse Graph Analytics Applications

Spara: An Energy-Efficient ReRAM-Based Accelerator for Spars...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Long Zheng Jieshan Zhao Yu Huang Qinggang Wang Zhen Zeng Jingling Xue Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology China UNSW Sydney Australia

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

Resistive random access memory (ReRAM) addresses the high memory bandwidth requirement challenge of graph analytics by integrating the computing logic in the memory. Due to the matrix-structured crossbar architecture, existing ReRAM-based accelerators, when handling real-world graphs that often have the skewed degree distribution, suffer from the severe sparsity problem arising from zero fillings and activation nondeterminism, incurring substantial ineffectual *** this paper, we observe that the sparsity sources lie in the consecutive mapping of source and destination vertex index onto the wordline and bitline of a crossbar. Although exhaustive graph reordering improves the sparsity-induced inefficiency, its totally-random (source and destination) vertex mapping leads to expensive overheads. This work exploits the insight in a mid-point vertex mapping with the random wordlines and consecutive bitlines. A cost-effective preprocessing is proposed to exploit the insight by rapidly exploring the crossbar-fit vertex reorderings but ignores the sparsity arising from activation dynamics. We present a novel ReRAM-based graph analytics accelerator, named Spara, which can maximize the workload density of crossbars dynamically by using a tightly-coupled bank parallel architecture further proposed. Results on real-world and synthesized graphs show that Spara outperforms GraphR and GraphSAR by 8.21 × and 5.01 × in terms of performance, and by 8.97 × and 5.68× in terms of energy savings (on average), while incurring a reasonable (

关键词： Indexes Electrodes Random access memory Parallel architectures Resistance Memory management

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A Heterogeneous PIM Hardware-Software Co-Design for Energy-Efficient Graph Processing

A Heterogeneous PIM Hardware-Software Co-Design for Energy-E...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Yu Huang Long Zheng Pengcheng Yao Jieshan Zhao Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology China UNSW Sydney Australia

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

Processing-In-Memory (PIM) is an emerging technology that addresses the memory bottleneck of graph processing. In general, analog memristor-based PIM promises high parallelism provided that the underlying matrix-structured crossbar can be fully utilized while digital CMOS-based PIM has a faster single-edge execution but its parallelism can be low. In this paper, we observe that there is no absolute winner between these two representative PIM technologies for graph applications, which often exhibit irregular workloads. To reap the best of both worlds, we introduce a new heterogeneous PIM hardware, called Hetraph, to facilitate energy-efficient graph processing. Hetraph incorporates memristor-based analog computation units (for high-parallelism computing) and CMOS-based digital computation cores (for efficient computing) on the same logic layer of a 3D die-stacked memory device. To maximize the hardware utilization, our software design offers a hardware heterogeneity-aware execution model and a workload offloading mechanism. For performance speedups, such a hardware-software co-design outperforms the state-of-the-art by 7.54 ×(CPU), 1.56 ×(GPU), 4.13× (memristor-based PIM) and 3.05× (CMOS-based PIM), on average. For energy savings, Hetraph reduces the energy consumption by 57.58× (CPU), 19.93× (GPU), 14.02 ×(memristor-based PIM) and 10.48 ×(CMOS-based PIM), on average.

关键词： Hardware Computer architecture Parallel processing Three-dimensional displays Computational modeling Graphics processing units Memristors

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