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A Single-Ended High-Voltage-Compliant 11-bit Current-Steering Digital-to-Analog Converter for Adaptive Noise Cancellation in Power Over Data Line networks

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第3期33卷 638-650页

作者： Burkhardt, Felix Protze, Florian Ellinger, Frank Tech Univ Dresden Chair Circuit Design & Network Theory D-01069 Dresden Germany

Automotive Ethernet is considered to be the backbone of future in-vehicle data communication. One main feature is its ability to simultaneously transmit data and energy via power over data lines (PoDL). This article proposes the design of a single-ended high-voltage (HV)-compliant 11-bit current-steering digital-to-analog converter (DAC). The converter is tailored for the utilization as digitally controlled current source in an adaptive noise-cancellation filter for PoDL networks. designed in an HV-compliant 180-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) semiconductor technology, the DAC features a monolithically combined topology of two identical 10-bit low-voltage (LV) current-steering DACs supplied at 1.8 V and two complementary HV-compliant output current stages. Main design features of the segmented LV DAC are the utilization of single-ended current cells with an optimized switching logic, proposed to enhance the cells transient performance and energy efficiency. Furthermore, a newly derived $Q<^>4$ asymmetric rotated walk switching scheme is investigated. At a maximum output voltage of 60 V, the proposed DAC can deliver a bidirectional output current with the amplitudes of up to 500 mA. The proposed DAC exhibits the highest voltage compliance combined with the highest output current compared with related works. It also features the second highest resolution. Operated at a sample rate of 10 MS/s with a resolution of 11 bit, a spurious-free dynamic range (SFDR) of 57.8 dB could be measured for a synthesized single tone at 100 kHz, as well as a maximum integral nonlinearity (INL) error of 1.61 LSB and a differential nonlinearity (DNL) error of 1.05 LSB.

关键词： Couplings Finite impulse response filters Switches Low-pass filters Attenuation Inductors Adaptive systems Voltage control Thermometers Noise cancellation Automotive Ethernet current steering digital-to-analog converter (DAC) high voltage (HV) power over data lines (PoDL) single-ended switching scheme

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Microstrip-Based Anti-Aliasing Filters for Beyond-50 GHz-Bandwidth Mix-Filter-Sample Analog-to-Digital-Converters

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IEEE ACCESS 2025年 13卷 65389-65402页

作者： Lorenz, Anton Matthus, Christian D. Ellinger, Frank Tech Univ Dresden Chair Circuit Design & Network Theory D-01069 Dresden Germany

High performance anti-aliasing filters (AAF) are critical components of advanced frequency interleaved (FI) analog-to-digital converter (ADC) structures, which are capable of overcoming the sample-clock jitter limit for ultra-high speed power efficient ADCs exceeding 100GS/s as is necessary in future radio frequency systems. Employing printed circuit board (PCB) microstrip filters is a promising approach as they offer a highly precise low-cost solution. In face of the specific requirements of the FI-ADC on the AAF amplitude response, the stepped impedance approach is shown to be much more suitable than other common approaches for wide stop band filters. The solution to neutralizing the spurious pass bands by placing them in the samplers' mute frequency regions is introduced. Due to the high cutoff frequencies, typically beyond 8GHz, parasitics and lateral resonances become significant however. Hence, a novel compensation method is presented that integrates well with the required amplitude response, by reinterpreting the longitudinal low-Z-sections as individual lateral microstrips. To prove the proposed method, the design, simulation, and physical implementation of such AAFs are carried out in the context of a state-of-the-art beyond-20GS/s 7bit sub-ADC core and a baseband processing bandwidth of 7GHz. The measurement results confirm the behavior predicted by the analytical models and EM simulations, and therefore the suitability of the method for designing AAFs for FI-ADCs.

关键词： Filters Microstrip filters Finite impulse response filters Printed circuits Mixers Impedance Jitter Frequency response Clocks Baseband Analog-to-digital converter (ADC) anti-aliasing filter frequency interleaving microstrip stepped impedance filter

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A V -Band 2-Gb/s 6.5-dBm Low-Power Transmitter in CMOS With On-Chip Antenna and Consumption Adaptivity Down to 700 nW

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IEEE JOURNAL OF SOLID-STATE circuitS 2025年第2期60卷 410-420页

作者： An, Xin Morath, Helmuth P. E. Protze, Florian Wagner, Jens Ellinger, Frank Tech Univ Dresden Chair Circuit Design & Network Theory CCN Ctr Tactile Internet Human In the Loop CeTI D-01069 Dresden Germany

This article presents and investigates a V -band transmitter (TX) for low-power wireless communication supporting on-off keying (OOK) and four-/eight-level pulse amplitude modulation (PAM4/8). To prove the concept, the circuit is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) complementary metal oxide semiconductor (CMOS) technology. The TX consumes 11.7 mW at full speed. Furthermore, the TX supports low-power mode with as low as 700 nW of dc power. The maximum data rate is 2 Gb/s. By applying dynamic data rate to dc-power adaptivity (DDDA), the dc power can be significantly reduced as the data rates decreases. This maintains the energy-per-bit below 10 pJ/b for data rates greater than 100 kb/s with a best value of 3.9 pJ/b and allows the dc power to be greatly reduced down to 700 nW at data rates below 20 kb/s. The measured maximum transmission power is 6.5 dBm. Moreover, the TX achieves 10-dBm effective isotropic radiated power (EIRP) with an on-chip 3-D antenna. The core area of the TX is only 0.19 mm 2 . To the best knowledge of the authors, the proposed TX is the first reported TX with DDDA and achieves the lowest dc power in comparison to similar designs that have been reported to date.

关键词： Wireless sensor networks Wireless communication System-on-chip Power amplifiers Logic gates Power harmonic filters Voltage-controlled oscillators Bondwire antenna consumption adaptivity duty cycling millimeter-wave (mmW) on-off keying (OOK) pulse amplitude modulation (PAM) wireless sensor network (WSN) wireless sensor network (WSN)

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design and Implementation of Low-Power Injection-Locked Ring Oscillators: Start-Up Time Analysis and Phase Noise Enhancement 16

Design and Implementation of Low-Power Injection-Locked Ring...

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16th IEEE Latin American Symposium on circuits and Systems, LASCAS 2025

作者： Seyyedrezaei, Seyyedmohsen Wagner, Jens Ellinger, Frank Technische Universität Dresden Chair for Circuit Design and Network Theory Germany Germany

ISBN: (纸本)9798331522124

This paper presents an analysis of the start-up time and injection locking in ring oscillators and develops a mathematical model for the start-up time. Two low-power CMOS-based voltage-controlled injection-locked ring oscillators (VCILROs)-a three-stage and a nine-stage-are designed and fabricated in standard 130 nm BiCMOS technology to validate the theory and compare their performance. Using the frequency tunability feature acquired by employing a variable RC network, the VCILRO provides the calibration feature to compensate for process, voltage, and temperature (PVT) variations. The oscillation frequency of both presented VCILROs can be locked to the injected reference signal to improve frequency stability. The three-stage and nine-stage oscillators are powered from a 0. 9V supply and consume 8.9 μ W and 76.8 μ W of DC power at 50 MHz. The three-stage and nine-stage VCILROs occupy areas of 0.0015 mm2and 0.0048 mm2, respectively. C © 2025 IEEE.

关键词： Vibrators

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Analysis of KVCO Variation in a Triple-Ism-Band Voltage-Controlled Ring Oscillator With Dual Frequency Tuning Mechanisms 16

Analysis of KVCO Variation in a Triple-Ism-Band Voltage-Cont...

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16th IEEE Latin American Symposium on circuits and Systems, LASCAS 2025

作者： Seyyedrezaei, Seyyedmohsen Wagner, Jens Ellinger, Frank Technische Universität Dresden Chair for Circuit Design and Network Theory Dresden Germany

ISBN: (纸本)9798331522124

This paper presents the analysis and design of a three-stage low-power CMOS-based voltage-controlled ring oscillator (VCRO) fabricated in standard 130 nm BiCMOS technology. Using the fine and coarse frequency tunability features acquired by employing a variable RC network, the VCRO can work in three different industrial, scientific, and medical (ISM) bands. The theoretical model, corroborated by measurements, demonstrates that incorporating both capacitive and resistive frequency tuning features allows the VCRO to adapt its voltage-controlled oscillator gain (KVCO) variation according to demand. This makes the presented ring oscillator suitable for a broad spectrum of applications such as phase-locked loops (PLLs), where the voltage-controlled oscillator (VCO) must meet strict criteria. The VCRO is powered by a 0.75 V supply and consumes only 1.7 μ ~W, 3.5 μ ~W, and 5.7 μ ~W of DC power at 13.56 MHz, 27.12 MHz, and 40.68 MHz ISM frequencies, respectively. The circuit core occupies an area of 0.0012 ~mm2. © 2025 IEEE.

关键词： CMOS integrated circuits

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A 48 MHz Crystal Oscillator with Dynamic Negative Resistance and Initial Current Boosting Fast Start-Up Techniques 16

A 48 MHz Crystal Oscillator with Dynamic Negative Resistance...

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16th IEEE Latin American Symposium on circuits and Systems, LASCAS 2025

作者： Seyyedrezaei, Seyyedmohsen Wagner, Jens Ellinger, Frank Technische Universität Dresden Chair for Circuit Design and Network Theory Germany Germany

ISBN: (纸本)9798331522124

This paper presents a low-power and fast start-up crystal oscillator (XO) operating at 48 MHz. To reduce the start-up time (Ts) required to oscillate the crystal (XTAL) resonator, the XO uses a combination of two different techniques. A dynamic negative resistance boosting (DNRB) technique is utilized to efficiently control the duration of the boosted gm and total power consumption. In order to further improve the start-up speed, a novel technique to set the initial condition is used to increase the initial motional current amplitude. The proposed XO achieves a start-up time of 7.6 μ s while it is powered by a 0.85 V power supply and consumes 107 μ W of steady-state power and 1.9 nJ of start-up energy. The proposed techniques are implemented using CMOS transistors in 130 nm BiCMOS technology occupying an active area of 0.004 mm2. © 2025 IEEE.

关键词： Comparator circuits

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Ultra-Low-Power 0.35-V 0.63-nW/kHz Multi-Stacked Clock Oscillator With Adjustable Frequency and Duty-Cycling

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IEEE ACCESS 2025年 13卷 57994-58007页

作者： Seyyedrezaei, Seyyedmohsen Wagner, Jens Ellinger, Frank Tech Univ Dresden Chair Circuit Design & Network Theory D-01069 Dresden Germany Tech Univ Dresden Ctr Tactile Internet Human Inthe Loop CeTI D-01069 Dresden Germany

This paper presents the analysis, design, and characterization of an on-chip ultra-low-power clock oscillator for sensor nodes, implemented in 130nm BiCMOS technology. The design employs a multi-stacked inverter-based ring oscillator topology which utilizes variable RC features to tune the oscillation frequency. It is demonstrated that incorporating resistive coupling in the inverter stages helps to minimize frequency deviation around 12.1-13.5% for 10% of power supply variations and consequently achieves frequency stability improvement. To the best knowledge of the authors, this is the first time that a multi-stacked technique is utilized in the inverter stages of an oscillator to make the leakage current negligible reducing power consumption. With an adaptive delay line, the design is enabled to produce an adjustable duty-cycling output. The proposed oscillator consumes 510pW from a 0.35V power supply at 810 Hz operation frequency and achieves a power efficiency of 0.63 nW/kHz, positioning it among the most efficient Hz-to-kHz oscillators. The design occupies an area of 0.038mm(2).

关键词： Transistors Ring oscillators Power demand Leakage currents Clocks Stacking MOSFET System-on-chip circuit stability Inverters Clock generation clock oscillator duty-cycling leakage current low voltage relaxation oscillator ring oscillator stacking technique ultra-low power consumption

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Energy-Efficient Aggressive Duty-Cycling of V-Band Power Amplifiers

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IEEE ACCESS 2025年 13卷 64638-64652页

作者： Becker, Maximilian Gottfried Gunia, Marco Mendez, Diego Ellinger, Frank Tech Univ Dresden Chair Circuit Design & Network Theory CCN D-01069 Dresden Germany Pontificia Univ Javeriana Elect Engn Dept Bogota 110231 Colombia Tech Univ Dresden Ctr Tactile Internet Human In the Loop CeTI D-01069 Dresden Germany

In addition to implementing the core functionality, a design goal for modern circuits is reduced energy consumption. When options for improving active state efficiency are eventually exhausted, the next step is to aggressively minimize the duration a circuit is active to reduce overall energy consumption. Consequently, this article presents a top-down study on efficient duty-cycling of power amplifiers (PAs), spanning system-level considerations down to experimental measurements of a proposed V-band PA. A thorough analysis of the duty-cycling characteristics in a wireless transmitter reveals the significance of fast and efficient switching, particularly if minimal latency is desired and if energy consumption should scale linearly with required data rate. To be able to assess PAs in that regard, the related key characteristics as well as transient RF power measurements are discussed. To enable aggressive duty-cycling at circuit level, the switching process is studied for integrated millimeter-wave (mmWave) class-E PAs. Despite intrinsic switched mode operation at RF, transitions from sleep to active state are not instantaneous, but two phases are revealed: operating point switching (OPS) and large-signal rise in the load network. A kickstarter circuit for speeding up this transition is investigated. To prove these concepts, a two-stage 51 GHz 14 dBm SiGe PA capable of fast and efficient operational state switching is designed and fabricated. Its duty-cycling performance is measured in detail for both single-tone and modulated signals showing turn-on times in the nanosecond range. The results demonstrate highly efficient duty-cycling of data transmission at a cycle duration of just 1 mu s for minimum latency. This article aims to allow system and circuit designers to better evaluate requirements for and performance of switchable mmWave PAs in context of duty-cycled communications.

关键词： BiCMOS integrated circuits duty-cycling class-E class-E mmWave mmWave power amplifiers power amplifiers transmitter transmitter transmitter

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FR4-Based Microstrip Anti-Aliasing Filters for Ultra-High-Speed Analog-To-Digital Converters

FR4-Based Microstrip Anti-Aliasing Filters for Ultra-High-Sp...

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German Microwave Conference

作者： Christian D. Matthus Anton Lorenz Frank Ellinger Chair for Circuit Design and Network Theory TU Dresden Germany

ISBN: (数字)9783982039749

ISBN: (纸本)9798331521790

In this work, passive low-pass filters implemented with microstrip transmission lines are investigated for their usability in ultra-high-speed analog-to-digital converters. Compared to other works which utilize expensive radio-frequency (RF) specified substrates based on e.g., ceramics, the most-frequently used material for printed circuit boards (PCBs) FR4 is used in this work. The filters were designed using analytical estimations and electro-magnetic field (EM) simulations. The most promising filter structures are high-order Chebyshev and Legendre type filters. We designed them conventionally and with additional stubs acting as band stop filters to suppress spurious passbands. The filters were physically implemented and measured up to a frequency of 67 GHz and show good performance with a high stopband attenuation for critical frequencies of more than 45 dB and a high skirt steepness. The insertion losses between 1.8 dB and 2.1 dB are slightly higher than those of the reference filters. On the other hand, the effect of spurious passbands is less severe for FR4. These effects are discussed in detail and a comparison to the more expensive RO4350B-filter counterparts is given.

关键词： Radio frequency Microstrip filters Filters Printed circuits Insertion loss Transmission line measurements Frequency measurement Passband Usability Substrates

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A Low Power BiCMOS UWB LNA with Reduced Chip Area for Sustainable IoT Electronics

A Low Power BiCMOS UWB LNA with Reduced Chip Area for Sustai...

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German Microwave Conference

作者： Toni Günter Stenzel Franz Alwin Dürrwald Naglaa El Agroudy Frank Ellinger Chair for Circuit Design and Network Theory Technische Universität Dresden Germany

ISBN: (数字)9783982039749

ISBN: (纸本)9798331521790

A low power, inductor-free, two-stage UWB LNA was designed and fabricated in 130nm SiGe BiCMOS technology. The proposed cascadation of a common-base and a common-collector stage with negative feedback enables high gain, wideband active matching and adequate linearity, consuming only 2.9mW. The measured gain S 21 is higher than 10.8dB while the noise figure NF stays below 5.3dB over the entire frequency range. Including AC coupling capacitors, the total chip area is less than 0.021mm 2 . Considering the low power and chip area requirements, the presented LNA provides superior performance to enable the next generation of sustainable RF circuits for IoT applications.

关键词： Couplings Wireless communication Radio frequency Semiconductor device measurement Capacitors BiCMOS integrated circuits Frequency measurement Internet of Things Wideband Silicon germanium

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