In a knowledge-based speech recognition system, landmarks are key points in time in the speech waveform. They guide the search for the underlying distinctive features. The effect of background noise on the automatic d...
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A new concept for packaging high frequency monolithic circuits is presented, It consists of developing miniaturized housings to shield individual passive components (e.g. CPW based), active elements, or combinations o...
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A new concept for packaging high frequency monolithic circuits is presented, It consists of developing miniaturized housings to shield individual passive components (e.g. CPW based), active elements, or combinations of them by employing silicon micromachining technology. At high frequencies, self-packaged configurations that are fabricated in this manner provide reduction in the overall size and weight of a circuit and provide increased isolation between neighboring circuits, Therefore, the resulting characteristics make these micropackaged components appropriate for high density, multilevel interconnect circuits. This paper will describe the fabrication procedures used to develop self-packaged components. Performance curves for typical high frequency circuit geometries that are implemented in this configuration are shown for measured and theoretical results.
New digital designs often include scan chains; high quality economical test is the reason. While many techniques exist for testing combinational circuitry, little attention has been paid to testing the sequential elem...
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New digital designs often include scan chains; high quality economical test is the reason. While many techniques exist for testing combinational circuitry, little attention has been paid to testing the sequential elements (latches and flip-flops). This paper presents techniques for testing latches included in either shift registers or scan chains. We show that a test that applies all transitions to a latch-based shift register is an exhaustive functional test of all of the latches in the register. A more complex test is required for a scan chain. We present a procedure for deriving an exhaustive functional test of the latches in a scan chain. The shift register and scan chain tests presented do not depend on the latch implementation; they detect all detectable combinational defects (those that do not introduce additional states into a latch). We assume that only one latch is defective.
We apply the method of complexity regularization to learn concepts from large concept classes. The method is shown to automatically find the best balance between the approximation error and the estimation error. In pa...
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We apply the method of complexity regularization to learn concepts from large concept classes. The method is shown to automatically find the best balance between the approximation error and the estimation error. In particular, the error probability of the obtained classifier is shown to decrease as 0(/spl radic/(log n/n)) to the achievable optimum, for large nonparametric classes of distributions, as the sample size n grows. In pattern recognition, or concept learning, the value of a {0,1}-valued random variable Y is to be predicted based upon observing an R/sup d/-valued random variable X.
The issue of scalability is key to the success of massively parallel processing. Due to their distributed nature, message-passing multicomputers are appropriate for achieving scalar performance. However, the message-p...
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The issue of scalability is key to the success of massively parallel processing. Due to their distributed nature, message-passing multicomputers are appropriate for achieving scalar performance. However, the message-passing model lacks programmability due to difficulties encountered by the programmers to partition and schedule the computation over the processors and to establish efficient inter-processor communication in the user code. Therefore, this paper presents a compile-time scheduling heuristic, called BLS, that maps programs onto the processors of a message-passing multicomputer. In contrast to other methods proposed, BLS takes a more global approach in attempt to balance the tradeoff between exploiting parallelism and reducing communication overhead. To evaluate the effectiveness of BLS, simulation studies of scheduling SISAL programs are presented.
Iterative least-squares estimation requires accurate reflectance models to retrieve geometrical parameters of 3-D objects from an image projection. We investigate the use of separating the diffuse (body) reflection fr...
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Iterative least-squares estimation requires accurate reflectance models to retrieve geometrical parameters of 3-D objects from an image projection. We investigate the use of separating the diffuse (body) reflection from the specular (surface) reflection, where the latter is responsible for image highlights. The performance of several models has been analysed by comparing local higher-order derivatives of the least-squares error function. Experiments show that the (smooth) diffuse component yields the best convergence properties, while the (sharp) specular component cast be utilized to improve noise insensitivity.
Most algorithms proposed for controlling traffic prior to entering ATM networks are based on static mechanisms. Such static control mechanisms do not account for the dynamics of the user traffic or the network state. ...
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ISBN:
(纸本)9780818670886
Most algorithms proposed for controlling traffic prior to entering ATM networks are based on static mechanisms. Such static control mechanisms do not account for the dynamics of the user traffic or the network state. Some dynamic control algorithms have been proposed, but most of these algorithms are extremely complex and may make it difficult to provide real time control. In this paper, we present an adaptive rate control algorithm that has been implemented in hardware. The algorithm controls the traffic submitted by a source based on the indirectly observed average rate and burst size for the source. The algorithm is highly efficient and thereby provides real time control at high speed. Our implementation, in concert with flow control in the local area network, provides the basis for ATM-based high performance distributed systems.
This paper describes an adaptive active noise cancellation (ANC) system that is based on an output-whitening approach and is an extension of the work of Graupe and Efron on single point adaptive ANC. The controller wo...
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This paper describes an adaptive active noise cancellation (ANC) system that is based on an output-whitening approach and is an extension of the work of Graupe and Efron on single point adaptive ANC. The controller works by continually estimating the time-series parameters of the noise to be canceled and by forcing the cancellation network to follow the identified parameters, so that the output is whitened. To address the problem of wide-area cancellation, a system that consists of a weighted array of single point output-whitening cancellation systems is proposed. Each controller is chosen to cancel the local temporal effects of the noise, and the array weights are chosen to match the wavefront shape. A comparison of cancellations based on single-point and wide-area systems demonstrates the superiority of the wide-area system.
This paper presents an algorithm that allocates registers optimally for straight-line code running on a generic multi-issue computer. On such a machine, an optimal register allocation is one that minimizes the number ...
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ISBN:
(纸本)9780897916653
This paper presents an algorithm that allocates registers optimally for straight-line code running on a generic multi-issue computer. On such a machine, an optimal register allocation is one that minimizes the number of issue slots that the code requires. Optimal spill selection and load/store placement are used to minimize the number of additional issue slots needed, given a schedule for the non-memory reference instructions and a fixed number of available physical registers. The generic multi-issue machine model closely models the operation of vector and VLIW processors, and could be extended to model super-scalar processors. The algorithm uses dynamic programming to search the state space of feasible register allocations; implicit and explicit state pruning are used to make the problem tractable without sacrificing optimality. The optimal allocation produced by the algorithm for a substantial example is presented.
In this paper we make an analogy between the time that storage must be maintained in a optimistic simulation and the blocking time in a conservative simulation. By exploring this analogy, we design two new Global Virt...
ISBN:
(纸本)1565550277
In this paper we make an analogy between the time that storage must be maintained in a optimistic simulation and the blocking time in a conservative simulation. By exploring this analogy, we design two new Global Virtual Time (GVT) protocols for Time Warp systems. The first protocol is based on null message clock advancement in conservative approaches. Our main contribution is a new protocol inspired by Misra's circulating marker scheme for deadlock recovery. It is simple enough to be implemented in hardware, takes no overhead in the normal path, can be made to work over non-FIFO links, and its overhead can be dynamically tuned based on computational load.
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