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International Conference on Data Engineering

作者： Feng Cheng Jiang Xiao Cunyang Liu Shijie Zhang Yifan Zhou Bo Li Baochun Li Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Hong Kong University of Science and Technology Hong Kong University of Toronto Canada

ISBN: (数字)9798350317152

ISBN: (纸本)9798350317169

Directed Acyclic Graph (DAG)-based blockchain (a.k.a distributed ledger) has become prevalent for supporting highly concurrent applications. Its inherent parallel data structure accelerates block generation significantly, shifting the bottleneck from performance to storage scalability. An intuitive solution is to apply state sharding that divides the entire ledger (i.e., transactions and states) into multiple shards. While each node only stores proportional transactions, it suffers from the challenges of storing and ensuring the processing consistency of cross-shard transactions. In this paper, we propose SharDAG, a new mechanism that leverages adaptive sharding for DAG-based blockchains to achieve high performance and strong consistency. The key idea of SharDAG is to exploit unique characteristics - silent assets - and design a lightweight processing mechanism based on avatar account caching. Furthermore, we design a Byzantine resilient cross-shard verification mechanism with a theoretically optimal number of participating nodes, which guarantees the consistency and security of avatar account aggregation. Our comprehensive evaluations on real-world workloads demonstrate that SharDAG presents up to 3.8 x throughput improvement compared to the state-of-the-art and reduces the storage overhead of cross-shard transactions.

关键词： Sharding Directed acyclic graph Distributed ledger Avatars Scalability Receivers Throughput

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DarkSAM: Fooling Segment Anything Model to Segment Nothing 38

DarkSAM: Fooling Segment Anything Model to Segment Nothing

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38th Conference on Neural Information Processing Systems, NeurIPS 2024

作者： Zhou, Ziqi Song, Yufei Li, Minghui Hu, Shengshan Wang, Xianlong Zhang, Leo Yu Yao, Dezhong Jin, Hai National Engineering Research Center for Big Data Technology and System China Services Computing Technology and System Lab China Cluster and Grid Computing Lab China Hubei Engineering Research Center on Big Data Security China Hubei Key Laboratory of Distributed System Security China School of Computer Science and Technology Huazhong University of Science and Technology China School of Cyber Science and Engineering Huazhong University of Science and Technology China School of Software Engineering Huazhong University of Science and Technology China School of Information and Communication Technology Griffith University Australia

Segment Anything Model (SAM) has recently gained much attention for its outstanding generalization to unseen data and tasks. Despite its promising prospect, the vulnerabilities of SAM, especially to universal adversarial perturbation (UAP) have not been thoroughly investigated yet. In this paper, we propose DarkSAM, the first prompt-free universal attack framework against SAM, including a semantic decoupling-based spatial attack and a texture distortion-based frequency attack. We first divide the output of SAM into foreground and background. Then, we design a shadow target strategy to obtain the semantic blueprint of the image as the attack target. DarkSAM is dedicated to fooling SAM by extracting and destroying crucial object features from images in both spatial and frequency domains. In the spatial domain, we disrupt the semantics of both the foreground and background in the image to confuse SAM. In the frequency domain, we further enhance the attack effectiveness by distorting the high-frequency components (i.e., texture information) of the image. Consequently, with a single UAP, DarkSAM renders SAM incapable of segmenting objects across diverse images with varying prompts. Experimental results on four datasets for SAM and its two variant models demonstrate the powerful attack capability and transferability of DarkSAM. Our codes are available at: https://***/CGCL-codes/DarkSAM. © 2024 Neural information processing systems foundation. All rights reserved.

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On the Security of Smart Home Systems:A Survey

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Journal of Computer Science & Technology 2023年第2期38卷 228-247页

作者：袁斌万俊吴宇晗邹德清金海 School of Cyber Science and Engineering Huazhong University of Science and TechnologyWuhan 430074China Hubei Key Laboratory of Distributed System Security Huazhong University of Science and Technology Wuhan 430074China Hubei Engineering Research Center on Big Data Security Huazhong University of Science and Technology Wuhan 430074China National Engineering Research Center for Big Data Technology and System Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Lab Huazhong University of Science and TechnologyWuhan 430074China Shenzhen Huazhong University of Science and Technology Research Institute Shenzhen 518057China School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Lab Huazhong University of Science and TechnologyWuhan 430074China

Among the plethora of IoT(Internet of Things)applications,the smart home is one of the ***,the rapid development of the smart home has also made smart home systems a target for ***,researchers have made many efforts to investigate and enhance the security of smart home *** a more secure smart home ecosystem,we present a detailed literature review on the security of smart home ***,we categorize smart home systems’security issues into the platform,device,and communication *** exploring the research and specific issues in each of these security areas,we summarize the root causes of the security flaws in today's smart home systems,which include the heterogeneity of internal components of the systems,vendors'customization,the lack of clear responsibility boundaries and the absence of standard security ***,to better understand the security of smart home systems and potentially provide better protection for smart home systems,we propose research directions,including automated vulnerability mining,vigorous security checking,and data-driven security analysis.

关键词： IoT(Internet of Things) smart home IoT security smart home security

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Can Large Language Models Serve as Evaluators for Code Summarization?

arXiv

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arXiv 2024年

作者： Wu, Yang Wan, Yao Chu, Zhaoyang Zhao, Wenting Liu, Ye Zhang, Hongyu Shi, Xuanhua Yu, Philip S. Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Big Data and Social Computing Lab University of Illinois Chicago Chicago United States Salesforce Research Palo Alto United States School of Big Data and Software Engineering Chongqing University Chongqing China

Code summarization facilitates program comprehension and software maintenance by converting code snippets into natural-language descriptions. Over the years, numerous methods have been developed for this task, but a key challenge remains: effectively evaluating the quality of generated summaries. While human evaluation is effective for assessing code summary quality, it is labor-intensive and difficult to scale. Commonly used automatic metrics, such as BLEU, ROUGE-L, METEOR, and BERTScore, often fail to align closely with human judgments. In this paper, we explore the potential of Large Language Models (LLMs) for evaluating code summarization. We propose CODERPE (Role-Player for Code Summarization Evaluation), a novel method that leverages role-player prompting to assess the quality of generated summaries. Specifically, we prompt an LLM agent to play diverse roles, such as code reviewer, code author, code editor, and system analyst. Each role evaluates the quality of code summaries across key dimensions, including coherence, consistency, fluency, and relevance. We further explore the robustness of LLMs as evaluators by employing various prompting strategies, including chain-of-thought reasoning, in-context learning, and tailored rating form designs. The results demonstrate that LLMs serve as effective evaluators for code summarization methods. Notably, our LLM-based evaluator, CODERPE, achieves an 81.59% Spearman correlation with human evaluations, outperforming the existing BERTScore metric by 17.27%. © 2024, CC BY.

关键词： Software agents

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A Data-Centric Accelerator for High-Performance Hypergraph Processing 22

A Data-Centric Accelerator for High-Performance Hypergraph P...

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Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Qinggang Wang Long Zheng Ao Hu Yu Huang Pengcheng Yao Chuangyi Gui Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China and Zhejiang Lab Hangzhou China National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

ISBN: (纸本)9781665462723

Hypergraph processing has emerged as a powerful approach for analyzing complex multilateral relationships among multiple entities. Past research on building hypergraph systems suggests that changing the scheduling order of bipartite edge tasks can improve the overlap-induced data locality in hypergraph processing. However, due to the complex intertwined connections between vertices and hyperedges, it is almost impossible to find a locality-optimal scheduling order. Thus, these task-centric hypergraph systems often suffer from substantial off-chip *** this paper, we first propose a novel data-centric Load-Trigger-Reduce (LTR) execution model to exploit fully the locality in hypergraph processing. Unlike a task-centric model that loads the required data along with a task, our LTR model invokes tasks as per the data used. Specifically, once the hypergraph data is loaded into the on-chip memory, all of its relevant computation tasks will be triggered simultaneously to output intermediate results, which are finally reduced to update the final results. Our LTR model enables all hypergraph data to be accessed once in each iteration. To fully exploit the LTR performance potential, we further architect an LTR-driven hypergraph accelerator, XuLin, which features with an adaptive data loading mechanism to minimize the loading cost via chunk merging at runtime. XuLin is also equipped with a priority-based differential data reduction scheme to reduce the impact of conflicting updates on performance. We have implemented XuLin both on a Xilinx Alveo U250 FPGA card and using a cycle-accurate simulator. The results show that XuLin outperforms the state-of-the-art hypergraph processing solutions Hygra and ChGraph by 20.47× and 8.77× on average, respectively.

关键词： hypergraph data-centric accelerator

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Efficient mobile code offloading in heterogeneous wireless networks

Efficient mobile code offloading in heterogeneous wireless n...

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作者： Lu, Feng Liu, Ruoxue Li, Wei Jin, Hai Zomaya, Albert Y. Services Computing Technology and System Lab Big Data Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Center for Distributed and High Performance Computing School of Information Technologies The University of Sydney Sydney Australia

Mobile data offloading has already appeared to offer the means of addressing the challenges of limited computing capability and battery life of mobile devices. Most existing code offloading frameworks only consider migrating an application within a single network at a time and failed to fully utilize the energy efficiency mechanism of the latest CPU chips. To tackle these issues, we propose an offloading approach under both a multitasking environment and a heterogeneous network to increase energy and execution efficiency. The offloading problem was formulated as a biobjective optimization problem that aims to save energy and keep a good performance by combining mobile cloud computing with *** technology under a heterogeneous network equipped with cellular and WiFi connectivity. By varying the applications and network scenarios, the experimental results show that with offloading a single application using our proposed framework, the data-intensive application can obviously benefit when the access point density of WiFi reaches 0.0002 unit/m2. Under multiple application scenarios, our proposed framework can increase processing speed by an average of 0.3× over the single application and can save an average of 25% power over the single application. © 2019 John Wiley & Sons, Ltd.

关键词： Heterogeneous networks

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RAHP: A Redundancy-aware Accelerator for High-performance Hypergraph Neural Network

RAHP: A Redundancy-aware Accelerator for High-performance Hy...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Hui Yu Yu Zhang Ligang He Yingqi Zhao Xintao Li Ruida Xin Jin Zhao Xiaofei Liao Haikun Liu Bingsheng He Hai Jin National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Department of Computer Science University of Warwick United Kingdom National University of Singapore Singapore

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Hypergraph Neural Network (HyperGNN) has emerged as a potent methodology for dissecting intricate multilateral connections among various entities. Current software/hardware solutions leverage a sequential execution model that relies on hyperedge and vertex indices for conducting standard matrix operations for HyperGNN inference. Yet, they are impeded by the dual challenges of redundant computation and irregular memory access overheads. This is primarily due to the frequent and repetitive access and updating of a number of feature vectors corresponding to the same hyperedges and vertices. To address these challenges, we propose the first redundancy-aware accelerator, RAHP, which enables high performance execution of HyperGNN inference. Specifically, we present a redundancy-aware asynchronous execution approach into the accelerator design for HyperGNN to reduce redundant computations and off-chip memory accesses. To unveil opportunities for data reuse and unlock the parallelism that existing HyperGNN solutions fail to capture, it prioritizes vertices with the highest degree as roots, prefetching other vertices along the hypergraph structure to capture the common vertices among multiple hyperedges, and synchronizing the computations of hyperedges and vertices in real-time. By such means, this facilitates the concurrent processing of relevant hyperedge and vertex computations of the common vertices along the hypergraph topology, resulting in smaller redundant computations overhead. Furthermore, by efficiently caching intermediate results of the common vertices, it curtails memory traffic and off-chip communications. To fully harness the performance potential of our proposed approach in the accelerator, RAHP incorporates a topology-driven data loading mechanism to minimize off-chip memory accesses on the fly. It is also endowed with an adaptive data synchronization scheme to mitigate the effects of conflicting updates of both hyperedges and vertices. Moreover, RAHP emplo

关键词： Computational modeling Neural networks Memory management Loading Energy conservation Vectors Software Topology Synchronization Standards

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Design Automation Conference

作者： Jin Zhao Yu Zhang Jian Cheng Yiyang Wu Chuyue Ye Hui Yu Zhiying Huang Hai Jin Xiaofei Liao Lin Gu Haikun Liu National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Zhejiang-HUST Joint Research Center for Graph Processing Zhejiang Lab Hangzhou China

Temporal graph processing is used to handle the snapshots of the temporal graph, which concerns changes in graph over time. Although several software/hardware solutions have been designed for efficient temporal graph processing, they still suffer from serious irregular data access due to the uncoordinated graph traversal. To overcome these limitations, this paper proposes SaGraph, a domain-specific hardware accelerator to support the efficient processing of temporal graph. Specifically, temporal graph processing shows strong data access similarity, i.e., most graph accesses of the processing of different snapshots are the same and usually refer to a small fraction of vertices. SaGraph can dynamically coordinate the graph traversals and adaptively cache the vertex states to fully exploit the data access similarity for smaller data access overhead. We implemented and evaluated SaGraph on a Xilinx Alveo U280 FPGA card. Compared with the cutting-edge software and hardware solutions, SaGraph achieves 8.5×-157.3×, 4.2×-16.1× speedups and 34.7×-423.6×, 5.3×-14.7× energy savings, respectively.

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A Scalable, Efficient, and Robust Dynamic Memory Management Library for HLS-based FPGAs

A Scalable, Efficient, and Robust Dynamic Memory Management ...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Qinggang Wang Long Zheng Zhaozeng An Shuyi Xiong Runze Wang Yu Huang Pengcheng Yao Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Zhejiang Lab Hangzhou China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Nowadays, high-level synthesis (HLS) has gained prominence for FPGA-based architecture prototyping, enhancing productivity significantly. Despite this advancement, HLS tools are impeded by a critical drawback: they lack support for dynamic memory management (DMM), leading to static mem-ory allocation and suboptimal use of memory resources. In response, numerous efforts have been made to develop DMM solutions compatible with HLS. However, our analysis indicates that existing solutions fail to concurrently meet the desired trifecta of scalability (efficient management of memory of any size), efficiency (minimal latency in memory (de-)allocation), and robustness (low allocation failure rates). This limitation hampers their applicability in real-world scenarios. In this paper, we introduce GraDMM, a “three-birds-one- stone” solution that comprehensively enhances the scalability, efficiency, and robustness of DMM. The key insight is to formulate memory (de-)allocation as graph analytics and lever-age sophisticated FPGA-based graph processing techniques. To achieve scalability, GraDMM specializes a simplified pipeline that significantly suppresses resource utilization expansion caused by managed memory scaling. This is crucial for managing arbitrarily sized memory on resource-limited FPGA platforms. For efficiency, GraDMM implements a data-centric concurrent traversal scheme and a shortcut-assisted fast traversal policy to accelerate (de-)allocation-guided graph traversal, reducing mem-ory (de-)allocation latency. To enhance robustness, GraDMM incorporates an adaptive memory defragmenter that defragments managed memory to minimize fragmentation-induced allocation failures. GraDMM is encapsulated as a library, providing high- level interfaces for users and ensuring synthesizability with Vi- vado HLS. Experimental results demonstrate that GraDMM out-performs three state-of-the-art HLS-compatible DMM solutions by significant margins: 56.71 %-85.59% in resource consumption sa

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FaaSTube: Optimizing GPU-oriented Data Transfer for Serverless computing

arXiv

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arXiv 2024年

作者： Wu, Hao Deng, Junxiao Yu, Minchen Yu, Yue Liu, Yaochen Fan, Hao Wu, Song Wang, Wei National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Hong Kong University of Science and Technology Hong Kong The Chinese University of Hong Kong Shenzhen China

Serverless computing has gained significant traction for machine learning inference applications, which are often deployed as serverless workflows consisting of multiple CPU and GPU functions with data dependency. However, existing data-passing solutions for serverless computing primarily reply on host memory for fast data transfer, mandating substantial data movement and resulting in salient I/O overhead. In this paper, we present FaaSTube, a GPU-efficient data passing system for serverless inference. FaaSTube manages intermediate data within a GPU memory pool to facilitate direct data exchange between GPU functions. It enables fine-grained bandwidth sharing over PCIe and NVLink, minimizing data-passing latency for both host-to-GPU and GPU-to-GPU while providing performance isolation between functions. Additionally, FaaSTube implements an elastic GPU memory pool that dynamically scales to accommodate varying data-passing demands. Evaluations on real-world applications show that FaaSTube reduces end-to-end latency by up to 90% and achieves up to 12x higher throughput compared to the state-of-the-art. Copyright © 2024, The Authors. All rights reserved.

关键词： Computer graphics equipment

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